C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 81

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

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8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The C8051F52x/F52xA/F53x/F53xA family has a superset of all the peripherals included with a stan-
dard 8051. See Section “1. System Overview” on page 13 for more information about the available
peripherals. The CIP-51 includes on-chip debug hardware which interfaces directly with the analog and
digital subsystems, providing a complete data acquisition or control-system solution in a single integrated
circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 core includes the following features:
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput
256 Bytes of Internal RAM
Extended Interrupt Handler
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
Figure 8.1. CIP-51 Block Diagram
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
Rev. 1.4
TMP2
DATA BUS
DATA BUS
D8
D8
D8
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A16
D8
D8
D8
D8
Reset Input
Power Management Modes
Integrated Debug Logic
Program and Data Memory Security
B REGISTER
REGISTER
INTERRUPT
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
SFR
BUS
C8051F52x/F53x
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
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