C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 117

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

12.3. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
Note: See Section “12.1. Programming The Flash Memory” on page 113 for minimum V
ture requirements for flash erase and write operations.
12.4. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0). See example below.
Security Lock Byte:
1’s Complement:
Flash pages locked:
Addresses locked:
any other Flash
Locked when
set according
security lock
Access limit
to the Flash
pages are
locked
byte
'F520/0A/1/1A and 'F530/0A/1/1A
Unlocked Flash Pages
Lock Byte
Reserved
Figure 12.1. Flash Program Memory Map
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
0x0000 to 0x03FF (first two Flash pages)
0x1C00 to 0x1DFF in ’F520/0A/1/1A and ’F530/0A/1/1A
0x0C00 to 0x0FFF in ’F523/3A/4/4A and ’F533/3A/4/4A and 
0x0600 to 0x07FF in ’F526/6A/7/7A and ’F536/6A/7/7A
0x1E00
0x1DFF
0x1DFE
0x0000
0x1C00
'F523/3A/4/4A and 'F533/3A/4/4A
Rev. 1.4
Unlocked Flash Pages
Lock Byte
Reserved
0x0FFF
0x0FFE
0x0E00
0x0000
C8051F52x/F53x
'F526/6A/7/7A and 'F536/6A/7/7A
Unlocked Flash Pages
Flash memory organized
Lock Byte
Reserved
in 512-byte pages
DD
and tempera-
0x07FF
0x07FE
0x0600
0x0000
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