C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 22
C8051F526-IMR
Manufacturer Part Number
C8051F526-IMR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F526-IMR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
DFN-10
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
6
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
1500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
1.5. 12-Bit Analog to Digital Converter
The C8051F52x/F52xA/F53x/F53xA devices include an on-chip 12-bit SAR ADC with a maximum through-
put of 200 ksps. The ADC system includes a configurable analog multiplexer that selects the positive ADC
input, which is measured with respect to GND. Ports 0 and 1 are available as ADC inputs; additionally, the
ADC includes an innovative programmable gain stage which allows the ADC to sample inputs sources
greater than the VREF voltage. The on-chip Temperature Sensor output and the core supply voltage (V
are also available as ADC inputs. User firmware may shut down the ADC or use it in Burst Mode to save
power.
Conversions can be initiated in four ways: a software command, an overflow of Timer 1, an overflow of
Timer 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by
software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are
indicated by a status bit and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been
accumulated by a hardware accumulator. The resulting 12-bit to 16-bit data word is latched into the ADC
data SFRs upon completion of a conversion. When the system clock is slow, Burst Mode allows ADC0 to
automatically wake from a low power shutdown state, acquire and accumulate samples, then re-enter the
low power shutdown state without CPU intervention.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
22
Sensor
Temp
Analog Multiplexer
* Available on ‘F53x/
P0.6*
P0.7*
P1.0*
P1.7*
’F53xA devices
GND
VDD
P0.0
19-to-1
AMUX
Figure 1.7. 12-Bit ADC Block Diagram
Selectable
Gain
Configuration, Control, and Data Registers
Burst Mode
Logic
Rev. 1.4
ADC
12-Bit
SAR
End of
Conversion
Interrupt
Conversion
Start
16
Window Compare
Logic
Accumulator
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Rising Edge
Timer 2 Overflow
ADC Data
Registers
Window
Compare
Interrupt
DD
)
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