C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 109

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

*Note: Available only on the C8051F52x-C/F53x-C devices
ramp or during a brownout condition even when V
two possible ways to handle this transitional period as described below:
If using the on-chip regulator (REG0) at the 2.6 V setting (default), it is recommended that user software
set the VDDMON0 threshold to its high setting (V
VDMLVL bit to 1 in SFR Definition 11.1 (VDDMON). In this typical configuration, no external hardware or
additional software routines are necessary to monitor the V
Note: Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
If using the on-chip regulator (REG0) at the 2.1 V setting or if directly driving V
user system (software/hardware) should monitor V
two key parameters that can be affected when V
page 34) and minimum ADC tracking time (Table 2.3 on page 28).
SFR Definition 11.1. VDDMON: V
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–0: RESERVED. Read = Variable. Write = don’t care.
VDMEN VDDSTAT VDMLVL VDM1EN Reserved Reserved Reserved Reserved 1v010000
R/W
Bit7
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B. 
VDMEN: V
This bit turns the V
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2).
The V
ing the V
reset. See Table 2.8 on page 32 for the minimum V
0: V
1: V
VDDSTAT: V
This bit indicates the current power supply status (V
0: V
1: V
VDMLVL: V
0: V
1: V
system that includes code that writes to and/or erases Flash.
VDM1EN
This bit turns the V
source, and can generate a system reset.
0: Level-sensitive VDD Monitor Disabled.
1: Level-sensitive VDD Monitor Enabled (default).
DD
DD
DD
DD
DD
DD
Bit6
DD
R
Monitor Disabled.
Monitor Enabled (default).
is at or below the V
is above the V
Monitor (VDDMON0) Threshold is set to V
Monitor (VDDMON0) Threshold is set to V
Monitor can be allowed to stabilize before it is selected as a reset source. Select-
DD
*
: Level-sensitive V
DD
DD
monitor as a reset source before it has stabilized may generate a system
DD
Monitor Enable (VDDMON0).
Level Select.
Status.
R/W
Bit5
DD
DD
DD
monitor circuit on/off. The V
monitor circuit on/off. If turned on, it is also selected as a reset
Monitor (VDDMON0) Threshold.
DD
Bit4
DD
R
Monitor (VDDMON0) Threshold.
DD
Monitor Enable (VDDMON1).
Monitor Control
DD
Rev. 1.4
Bit3
RST-HIGH
R
DD
DD
< 2.0 V are: internal oscillator frequency (Table 2.11 on
is below the specified minimum of 2.0 V. There are
at power-on and also during device operation. The
) as soon as possible after reset by setting the
DD
RST-LOW
RST-HIGH
DD
Bit2
R
DD
level.
DD
Monitor cannot generate system
Monitor turn-on time.
Monitor output).
. This setting is required for any
(default).
C8051F52x/F53x
Bit1
R
DD
SFR Address:
with REG0 disabled, the
Bit0
R
Reset Value
0xFF
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