C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 158

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
SFR Definition 16.2. SPI0CN: SPI0 Control
158
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2: NSSMD1–NSSMD0: Slave Select Mode.
Bit1:
Bit0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) if a write to SPI0DAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. This
bit is not automatically cleared by hardware. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buf-
fer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Selects between the following NSS operation modes:
(See Section “16.2. SPI0 Master Mode Operation” on page 153 and Section “16.3. SPI0
Slave Mode Operation” on page 154).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
Bit6
MODF
R/W
Bit5
RXOVRN NSSMD1 NSSMD0
R/W
Bit4
Rev. 1.4
R/W
Bit3
R/W
Bit2
TXBMT
Bit1
R
SFR Address: 0xF8
SPIEN
R/W
Bit0
00000110
Addressable
Reset Value
Bit