C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 120

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
13. Port Input/Output
Digital and analog resources are available through up to 16 I/O pins. Port pins are organized as two or one
byte-wide Ports. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/out-
put; Port pins P0.0 - P2.7 can be assigned to one of the internal digital resources as shown in Figure 13.3.
The designer has complete control over which functions are assigned, limited only by the number of phys-
ical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the peripheral priority
order of the Priority Decoder (Figure 13.3 and Figure 13.4). The registers XBR0 and XBR1, defined in SFR
Definition 13.1 and SFR Definition 13.2, are used to select internal digital functions.
Port I/O pins are 5.25 V tolerant over the operating range of V
The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers
(PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 2.10 on
page 33.
120
Highest
Lowest
Priority
Priority
SYSCLK
Outputs
T0, T1
UART
P0
P1
PCA
CP0
SPI
LIN
(P0.0-P0.7)
(P1.0-P1.7*)
Figure 13.1. Port I/O Functional Block Diagram
2
4
2
7
2
8
8
2
Rev. 1.4
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
REGIN
. Figure 13.2 shows the Port cell circuit.
8
8
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
Cells
Cells
I/O
P0
P1
I/O
available on C8051F53x/
P1.0–1.7 and P0.7
C8051F53xA parts
PnMDIN Registers
PnMDOUT,
P0.0
P0.7
P1.7
P1.0