C8051F526-IMR Silicon Labs, C8051F526-IMR Datasheet - Page 212

• Manufacturer Part Number: C8051F526-IMR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C LIN 10Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F526-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: DFN-10
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 6
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
20.5. V
The calibration behavior of the internal voltage regulator (REG0) and its impact on V
(VDDMON0) high threshold setting differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
The following note applies to Revision A and Revision B devices: The output of the internal voltage reg-
ulator (REG0) is calibrated by the MCU immediately after any reset event. The output of the un-calibrated
internal regulator could be below the high threshold setting (V
this is the case and the V
power on reset, the MCU will remain in reset until a power-on reset (POR) occurs (i.e. V
keep the device in reset). A POR will force the V
teed to be below the un-calibrated output of the internal regulator. The device will then exit reset and
resume normal operation. It is for this reason Silicon Labs strongly recommends that the V
always left in the low threshold setting (i.e., default value upon POR).
When programming the Flash in-system, the V
setting. For the highest system reliability, the time the V
should be minimized (e.g., setting the V
operation and then changing it back to the low threshold setting immediately after the Flash write opera-
tion).
The following note applies to Revision C devices: The output of the internal voltage regulator (REG0) is
calibrated by the MCU immediately after a power-on reset (POR). This calibrated output setting will stay
calibrated through any type of reset other than POR. Because of this change in behavior of REG0, the “low
threshold” recommendation noted above for Revision A and Revision B devices does not apply to Revision
C devices; the V
application.
20.6. Reset Low Time
The maximum reset low time differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
Reset low time is the duration for which the RST pin is driven low by an external circuit while power is
applied to the device. On Revision A and Revision B devices with assembly build date code earlier than
1124 (year 2011, work week 24), the reset low time should be a maximum of 1 second. For longer reset
low times, a percentage of devices within a narrow range of temperatures (a 5 to 10 C window) may
“lock up” and fail to execute code. The condition is cleared only by cycling power.
Revision B devices with assembly date code 1124 or later and Revision C devices do not have any restric-
tions on reset low time.
20.7. Internal Oscillator Suspend Mode
The required bias setting for the internal oscillator before entering suspend mode differs between the sili-
con revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, firmware must set the ZTCEN bit in REF0CN (SFR Definition 5.1)
before entering suspend mode. If ZTCEN is not set to 1, there is a low probability of the device remaining
in suspend even when a wake-up condition is triggered. On Revision C devices, this bit need not be set to
1 before entering suspend mode.
212
DD
Monitor (VDDMON0) High Threshold Setting
DD
Monitor (VDDMON0) can be set to the high threshold as needed depending on the
DD
Monitor is set to the high threshold setting and if the MCU receives a non-
DD
Monitor to the high threshold setting just before the Flash write
DD
Rev. 1.4
DD
Monitor (VDDMON0) must be set to the high threshold
Monitor to the low threshold setting which is guaran-
DD
RST-HIGH
Monitor is set to the high threshold setting
) of the V
DD
Monitor (VDDMON0). If
DD
DD
DD
Monitor will
Monitor is
monitor