W25Q80BVSSIG Winbond Electronics, W25Q80BVSSIG Datasheet - Page 35

• Manufacturer Part Number: W25Q80BVSSIG
• Description: IC FLASH 8MBIT 8SOIC
• Manufacturer: Winbond Electronics

Specifications of W25Q80BVSSIG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 104MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4816329; T1015683

9.2.17
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are
not required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word
Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 16a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E3h instruction code, as shown in figure 16b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before
issuing normal instructions (See 9.2.20 for detail descriptions).
CLK
/CS
IO
IO
IO
IO
0
1
2
3
Mode 3
Mode 0
Octal Word Read Quad I/O (E3h)
Figure 16a. Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4
0
1
Instruction (E3h)
2
3
4
5
6
7
20
21
22
23
A23-16
8
16
17
18
19
- 35 -
9
12
13
14
15
A15-8
10
10
11
8
9
11
4
5
6
7
12
A7-0
0
1
2
3
13
Publication Release Date: October 06, 2010
4
5
6
7
14
M7-0
0
1
2
3
15
4
5
6
7
Byte 1
16
0
1
2
3
17
IOs switch from
Input to Output
4
5
6
7
Byte 2
18
W25Q80BV
0
1
2
3
19
≠
4
5
6
7
Byte 3
20
10)
0
1
2
3
21
Revision D
4
5
6
7
Byte 4