W25Q80BVSSIG Winbond Electronics, W25Q80BVSSIG Datasheet

IC FLASH 8MBIT 8SOIC

W25Q80BVSSIG

Manufacturer Part Number
W25Q80BVSSIG
Description
IC FLASH 8MBIT 8SOIC
Manufacturer
Winbond Electronics
Datasheet

Specifications of W25Q80BVSSIG

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
104MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4816329
T1015683

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W25Q80BV
8M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: October 06, 2010
- 1 -
Revision D

Related parts for W25Q80BVSSIG

W25Q80BVSSIG Summary of contents

Page 1

... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: October 06, 2010 - 1 - W25Q80BV Revision D ...

Page 2

... Status Register Protect (SRP1, SRP0).................................................................................13 9.1.8 Erase/Program Suspend Status (SUS) ................................................................................13 9.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................13 9.1.10 Quad Enable (QE) ..............................................................................................................14 9.1.11 Status Register Memory Protection (CMP = 0)...................................................................15 9.1.12 Status Register Memory Protection (CMP = 1)...................................................................16 9.2 INSTRUCTIONS................................................................................................................. 17 Table of Contents - 2 - W25Q80BV ...

Page 3

Manufacturer and Device Identification ................................................................................17 9.2.2 Instruction Set Table 1 (Erase, Program Instructions) ..........................................................18 9.2.3 Instruction Set Table 2 (Read Instructions) ..........................................................................19 9.2.4 Instruction Set Table 3 (ID, Security Instructions).................................................................20 9.2.5 Write Enable (06h)................................................................................................................21 9.2.6 Write Enable for Volatile ...

Page 4

Absolute Maximum Ratings................................................................................................ 61 10.2 Operating Ranges .............................................................................................................. 61 10.3 Power-up Timing and Write Inhibit Threshold .................................................................... 62 10.4 DC Electrical Characteristics.............................................................................................. 63 10.5 AC Measurement Conditions ............................................................................................. 64 10.6 AC Electrical Characteristics .............................................................................................. 65 10.7 AC Electrical Characteristics ...

Page 5

... Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. ...

Page 6

PIN CONFIGURATION SOIC 150 / 208-MIL / /WP ( GND Figure 1a. W25Q80BV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM DO (IO /WP ...

Page 7

PIN CONFIGURATION PDIP 300-MIL /CS DO (IO /WP (IO GND Figure 1c. W25Q80BV Pin Assignments, 8-pin PDIP 300-mil (Package Code DA) 6. PIN DESCRIPTION SOIC 150/208-MIL, WSON 6X5-MM, AND PDIP 300-MIL PIN NO. PIN NAME 1 / ...

Page 8

... Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2 ...

Page 9

... CLK SPI SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q80BV Serial Flash Memory Block Diagram 0000FFh 0000FFh xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh ...

Page 10

FUNCTIONAL DESCRIPTION 8.1 SPI OPERATIONS 8.1.1 Standard SPI Instructions The W25Q80BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...

Page 11

... Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...

Page 12

... The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits ...

Page 13

... CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. 9.1.7 ...

Page 14

Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set state (factory default), the /WP pin and ...

Page 15

... X Notes don’t care 2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. W25Q80BV (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 15 0F0000h – 0FFFFFh 14 and 15 0E0000h – 0FFFFFh 12 thru 15 0C0000h – 0FFFFFh 8 thru 15 080000h – ...

Page 16

... X Notes don’t care 2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. W25Q80BV (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES 0 thru 15 000000h – 0FFFFFh 0 thru 14 000000h – 0EFFFFh 0 thru 13 000000h – 0DFFFFh 0 thru 11 000000h – 0BFFFFh 0 thru 7 000000h – ...

Page 17

... This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...

Page 18

Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 INSTRUCTION NAME (CODE) Write Enable 06h Write Enable for 50h Volatile Status Register Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program ...

Page 19

Instruction Set Table 2 (Read Instructions) BYTE 1 INSTRUCTION NAME (CODE) Read Data 03h Fast Read 0Bh Fast Read Dual Output 3Bh Fast Read Quad Output 6Bh Fast Read Dual I/O BBh Fast Read Quad I/O EBh (7) Word ...

Page 20

... Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address BYTE 2 BYTE 3 dummy dummy dummy dummy A23-A8 A7-A0, M[7:0] A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy 00h 00h A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15– W25Q80BV BYTE 4 ...

Page 21

... The non-volatile Status Register bits described in section 9.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non- volatile bits ...

Page 22

Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into ...

Page 23

Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 ...

Page 24

To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. ...

Page 25

... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. ...

Page 26

Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F (see AC Electrical Characteristics). This is accomplished by adding eight R “dummy” clocks ...

Page 27

Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO twice the rate of standard SPI devices. The Fast ...

Page 28

Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO executed before the device will accept the Fast ...

Page 29

Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...

Page 30

Mode CLK Mode 0 A23 MSB / CLK IOs ...

Page 31

Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO clock are required ...

Page 32

Mode CLK Mode 0 A23- Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast ...

Page 33

Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required ...

Page 34

Mode 3 0 CLK Mode 0 A23- Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with “8/16/32/64-Byte ...

Page 35

Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As ...

Page 36

Mode CLK Mode 0 A23-16 A15 Figure 16b. Octal Word ...

Page 37

Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. ...

Page 38

... The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place performed on serial flash devices. ...

Page 39

... Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...

Page 40

... Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data ...

Page 41

... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

Page 42

... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

Page 43

... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

Page 44

... Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

Page 45

Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. ...

Page 46

Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the ...

Page 47

Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...

Page 48

Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To ...

Page 49

Mode CLK Mode 0 Instruction (ABh High Impedance DO ( MSB Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram 7 8 ...

Page 50

Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...

Page 51

Read Manufacturer / Device ID Dual I/O (92h) The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at ...

Page 52

Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...

Page 53

Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80BV device. The ID number can be used in conjunction with user software methods to help prevent ...

Page 54

... The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 33. For memory type and capacity values refer to Manufacturer and Device Identification table. ...

Page 55

Read SFDP Register (5Ah) The W25Q80BV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more ...

Page 56

Serial Flash Discoverable Parameter (Revision 1.1) Definition Table BYTE DATA ADDRESS SFDP Signature 00h 53h SFDP Signature 01h 46h SFDP Signature 02h 44h SFDP Signature 03h 50h SFDP Minor Revisions 04h 01h SFDP Major Revisions 05h 01h Number of Parameter ...

Page 57

Flash Size in Bits 84h FFh Flash Size in Bits 85h FFh Flash Size in Bits 86h 7Fh Flash Size in Bits 87h 00h Bit[7:5]=010 88h 44h Bit[4:0]=00100 Quad Input Quad Output Fast Read Opcode 89h EBh Bit[7:5]=000 8Ah 08h ...

Page 58

... The W25Q80BV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...

Page 59

... Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...

Page 60

... DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out ...

Page 61

ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ...

Page 62

Power-up Timing and Write Inhibit Threshold Parameter VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. VCC VCC (max) VCC (min) Reset State V WI Symbol t ...

Page 63

DC Electrical Characteristics PARAMETER SYMBOL IN (1) Input Capacitance C (1) Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...

Page 64

AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Input ...

Page 65

AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions except Read Data instruction (03h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for all instructions except Read Data instruction (03h) 3.0V-3.6V VCC & Industrial Temperature Clock frequency for Read Data ...

Page 66

AC Electrical Characteristics ( DESCRIPTION /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup ...

Page 67

Serial Output Timing /CS CLK tCLQV tCLQX tCLQX IO MSB OUT output 10.9 Serial Input Timing /CS tCHSL tSLCH CLK tDVCH IO input 10.10 /HOLD Timing /CS CLK /HOLD IO output IO input 10.11 /WP Timing /CS tWHSL /WP ...

Page 68

PACKAGE SPECIFICATION 11.1 8-Pin SOIC 150-mil (Package Code SN SEATING PLANE SEATING PLANE SYMBOL (3) E ( (4) ...

Page 69

SOIC 208-mil (Package Code SS) SYMBOL Min A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5.18 E1 5.13 ( 7.70 L 0.50 y --- θ 0° Notes: 1. Controlling ...

Page 70

PDIP 300-mil (Package Code DA) SYMBO L Min A --- A1 0.38 A2 3. 6.22 L 2.92 e 8.51 B θ 0° ° MILLIMETERS Nom Max Min --- 5.33 --- --- --- 0.015 3.30 ...

Page 71

WSON 6x5mm (Package Code ZP) SYMBOL Min A 0.70 A1 0.00 b 0.35 --- C D 5.90 D2 3.35 E 4.90 E2 4.25 ( 0.55 y 0.00 MILLIMETERS Nom Max Min 0.75 0.80 0.028 0.02 0.05 ...

Page 72

WSON 6x5mm Cont’d. SYMBOL Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not ...

Page 73

... ORDERING INFORMATION W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 80B = 8M-bit V = 2. 8-pin SOIC 150-mil DA = 8-pin PDIP 300-mil I = Industrial (-40°C to +85° Automotive (-40°C to +105°C) (3, Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Green Package with Status Register Power-Down & OTP enabled Notes: 1. The “ ...

Page 74

... For WSON packages, the package type ZP is not used in the top side marking. 2. Package type SN (SOIC8 150mil special order package, please contact Winbond for ordering information. 3. For Automotive Temperature parts, please contact Winbond for availability. PRODUCT NUMBER W25Q80BVSNIG W25Q80BVSNIP W25Q80BVSSIG W25Q80BVSSIP W25Q80BVZPIG W25Q80BVZPIP W25Q80BVDAIG W25Q80BVDAIP (3) : ...

Page 75

... D 10/06/10 Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life ...

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