MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 78

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

Electrical Characteristics
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in
78
At recommended operating conditions (see
At recommended operating conditions (see
Unit Interval
Minimum Tx eye width
Tx RMS deterministic
jitter > 1.5 MHz
Tx RMS deterministic
jitter < 1.5 MHz
AC coupling capacitor
Notes:
Unit Interval
Max Rx inherent timing
error
Maximum time between
the jitter median and
maximum deviation from
the median
Max Rx inherent
deterministic timing error
Max Rx inherent
deterministic timing error
Note:
Parameter
Parameter
Table 35. PCI Express 2.0 (5.0 Gbps) Differential Transmitter (Tx) Output AC Specifications
1.
2.
3.
4.
No test load is necessarily accosted with this value.
Table 36. PCI Express 2.0 (5.0 Gbps) Differential Receiver (Rx) Input AC Specifications
No test load is necessarily associated with this value.
Specified at the measurement point into a timing and voltage test load as shown in
consecutive Tx UIs.
A T
Transmitter collected over any 250 consecutive Tx UIs. The T
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value.
The DSP device SerDes transmitter does not have a built-in C
TX-EYE
= 0.75 UI provides for a total sum of deterministic and random jitter budget of T
T
T
T
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
T
RX-DJ-DD-CC
RX-DJ-DD-DC
TX-HF-DJ-DD
T
T
Symbol
TX-LF-RMS
Symbol
T
RX-TJ-CC
RX-TJ-DC
TX-EYE
C
UI
UI
TX
Table
Table
4).
4).
199.94 200.00 200.06
199.40 200.00 200.06
0.75
Min
Min
75
—
—
—
—
—
—
Nom
Nom
3.0
—
—
—
—
—
—
—
Max
0.15
Max
0.34
0.30
0.24
200
0.4
—
—
TX-EYE-MEDIAN-to-MAX-JITTER
TX
. An external AC coupling capacitor is required.
Units
Units
nF
ps
UI
ps
ps
ps
UI
UI
UI
UI
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
The maximum Transmitter jitter can be
derived as:
T
See notes 2 and 3.
—
Reference input clock RMS jitter (< 1.5 MHz)
at pin < 1 ps
All transmitters must be AC coupled. The AC
coupling is required either within the media
or within the transmitting component itself.
See note 4.
Each UI is 400 ps ±300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
The maximum inherent total timing error for
common REF_CLK Rx architecture
Max Rx inherent total timing error
The maximum inherent deterministic timing
error for common REF_CLK Rx architecture
The maximum inherent deterministic timing
error for common REF_CLK Rx architecture
Figure
TX-MAX-JITTER
Figure 15
15.
TX-MAX-JITTER
median is less than half of the total
and measured over any 250
= 1 – T
Comments
Conditions
Freescale Semiconductor
TX-EYE
= 0.25 UI for the
= 0.25 UI.