MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 71

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

Freescale Semiconductor
MCSn output hold with respect to MCK
MCK to MDQS Skew
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to MDQS
MDQS preamble
MDQS postamble
Notes:
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
• > 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
1.
2.
3.
4.
5.
6.
The symbols used for timing specifications follow the pattern of t
and t
the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t
symbolizes DDR timing (DD) for the time t
setup (S) or output valid time. Also, t
low (L) until data outputs (D) are invalid (X) or data output hold time.
All MCK/MCK referenced measurements are made from the crossing of the two signals.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
Note that t
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same
adjustment value. See the MSC8157 Reference Manual for a description and understanding of the timing modifications enabled
by use of these bits.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8157.
At recommended operating conditions with V
For the ADDR/CMD setup and hold specifications in
control register is set to adjust the memory clocks by ½ applied cycle.
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
Table 30. DDR SDRAM Output AC Timing Specifications (continued)
DDKHMH
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
follows the symbol conventions described in note 1. For example, t
DDKLDX
MCK
symbolizes DDR timing (DD) for the time t
DDDDR
memory clock reference (K) goes from the high (H) state until outputs (A) are
Symbol
t
t
t
t
t
t
t
t
DDKHMH
DDKHDS,
DDKHDX,
DDKHCX
DDKHMP
DDKHME
DDKLDS
DDKLDX
NOTE
(1.5 V) ± 5%.
1
for outputs. Output hold time can be read as DDR timing (DD) from
(first two letters of functional block)(signal)(state) (reference)(state)
Table
0.9 × t
0.4 × t
–0.245
–0.375
0.606
0.675
0.744
0.917
1.10
–0.6
Min
250
275
300
375
450
250
275
300
375
450
30, it is assumed that the clock
MCK
MCK
DDKHMH
DDKHMH
MCK
0.6 × t
memory clock reference (K) goes
0.245
0.375
can be modified through control of
Max
0.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
describes the DDR timing (DD)
MCK
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
DDKHAS
for inputs
Notes
5, 6
—
—
3
4
5
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