MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 58

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

Electrical Characteristics
The characteristics of the clock signals are as follows:
3.5.2.3
Figure 4
3.5.2.4
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss can be large enough to degrade the eye opening
at the receiver beyond that allowed by the specification. To offset a portion of these effects, equalization can be used. The
following is a list of the most commonly used equalization techniques:
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The supply voltage requirements for
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLK[1–2] and SD_REF_CLK[1–2] are internally AC-coupled differential inputs as shown in
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA)
— If the device driving the SD_REF_CLK[1–2] and SD_REF_CLK[1–2] inputs cannot drive 50 Ω to
The input amplitude requirement is described in detail in the following sections.
shows the reference circuits for SerDes data lane transmitter and receiver.
Pre-emphasis on the transmitter
Figure
termination to
single-ended mode descriptions below for detailed requirements.
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
while the minimum common mode input level is 0.1 V above
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled
externally.
SerDes Transmitter and Receiver Reference Circuits
Equalization
Note: The [A–J] indicates the specific SerDes lane. Each lane can be assigned to a specific
Transmitter
3. Each differential clock input (SD_REF_CLK[1–2] or SD_REF_CLK[1–2] has on-chip 50-Ω
protocol by the RCW assignments at reset (see the MSC8157 Reference Manual
for details). External AC coupling capacitors are required for all protocols for all lanes.
Figure 4. SerDes Transmitter and Receiver Reference Circuits
SXCVSS
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
50 Ω
50 Ω
followed by on-chip AC-coupling.
SD_[A–J]_TX
SD_[A–J]_TX
V
DDSXC
are as specified in
SD_[A–J]_RX
SD_[A–J]_RX
Table
GND
4.
SXC
. For example, a clock with a 50/50 duty
50 Ω
50 Ω
Receiver
Freescale Semiconductor
GND
SXC
DC or