MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 74

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

Electrical Characteristics
3.6.2.1
Table 32
74
At recommended operating conditions (see
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]
frequency range
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] clock
frequency tolerance
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]
reference clock duty cycle
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]max
deterministic peak-peak jitter at 10
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] total
reference clock jitter at 10
jitter at ref_clk input)
SD_REF_CLK/SD_REF_CLK rising/falling edge
rate
Differential input high voltage
Differential input low voltage
Rising edge rate (SD_REF_CLKn to falling edge
rate)
Notes:
• Serial RapidIO, CPRI, SGMII
• PCI Express interface
lists AC requirements for the SerDes reference clocks.
1.
2.
3.
4.
5.
6.
7.
Only 100, 122.88, and 125 MHz have been tested. CPRI uses 122.88 MHz. The other interfaces use 100 or 125 MHz. Other
values do not work correctly with the rest of the system.
Limits are from PCI Express CEM Rev 2.0.
Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See
Measurement taken from differential waveform.
Measurement taken from single-ended waveform.
Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rising edge rate
of SD_RF_CLKn should be compared to the falling edge rate of SD_REF_CLKn; the maximum allowed difference should not
exceed 20% of the slowest edge rate. See
REF_CLK jitter must be less than 0.05 UI when measured against a Golden PLL reference. The Golden PLL must have a
maximum baud rate bandwidth greater than 1667, with a maximum 20 dB/dec rolloff down to a baud rate of 16.67 with no
peaking around the corner frequency.
AC Requirements for SerDes Reference Clock
Table 32. SD_REF_CLK[1–2] and SD_REF_CLK[1–2] Input Clock Requirements
Parameter
-6
BER (peak-to-peak
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
-6
BER
Table
4).
Figure
t
Figure
CLKRR
13.
t
t
CLK_DUTY
Rise-Fall
t
Symbol
CLK_REF
CLK_TOL
t
t
CLK_DJ
CLK_TJ
V
V
/t
IH
14.
IL
CLKFR
–100
–300
Min
200
40
—
—
—
—
—
1
CPRI: 122.88
100/125
Nom
—
—
—
—
—
—
—
—
50
Freescale Semiconductor
–200
Max
100
300
42
86
20
—
—
60
4
Units
MHz
ppm
ppm
V/ns
mV
mV
ps
ps
%
%
Notes
5, 6
—
—
1
2
3
4
4
4