MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 59

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

3.5.3
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, the CPRI data lines, and the SGMII data lines.
3.5.3.1
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Freescale Semiconductor
•
•
•
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
A passive high-pass filter network placed at the receiver, often referred to as passive equalization
The use of active circuits in the receiver, often referred to as adaptive equalization
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Figure 5. Differential Reference Clock Input DC Requirements (External DC-Coupled)
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
average voltage (common mode voltage) as between 100 mV and 400 mV.
clock input requirement for DC-coupled connection scheme.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GND
swing below and above the command mode voltage GND
requirement for AC-coupled connection scheme.
DC-Level Requirements for SerDes Interfaces
DC-Level Requirements for SerDes Reference Clocks
200 mV < Input Amplitude or Differential Peak < 800 mV
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
SXC
. Each signal wire of the differential inputs is allowed to
SXC
.
Figure 6
shows the SerDes reference clock input
Figure 5
100 mV < Vcm < 400 mV
shows the SerDes reference
Electrical Characteristics
Vmax < 800 mV
Vmin > 0 V
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