MSC8157ETVT1000A Freescale Semiconductor, MSC8157ETVT1000A Datasheet - Page 57

• Manufacturer Part Number: MSC8157ETVT1000A
• Description: Digital Signal Processors & Controllers - DSP, DSC Qual 8157 EN FG 1GHz -45 to 105c
• Manufacturer: Freescale Semiconductor

Specifications of MSC8157ETVT1000A

• Rohs: yes
• Core: SC3850
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 0.97 V to 1.05 V
• Maximum Operating Temperature: + 105 C
• Package / Case: FCPBGA-783
• Mounting Style: SMD/SMT

To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (V
the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In
other words, V
The peak-to-peak differential voltage (V
3.5.2.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SD_REF_CLK1/SD_REF_CLK1 or SD_REF_CLK2/SD_REF_CLK2.
Figure 3
Freescale Semiconductor
Differential Peak Voltage, V
Differential Peak-to-Peak, V
Differential Waveform
Common Mode Voltage, V
shows a receiver reference diagram of the SerDes reference clocks.
OD
Term
SerDes Reference Clock Receiver Characteristics
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V
cm
DIFFp
DIFFp-p
MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 1
Table 10. Differential Signal Definitions (continued)
Figure 3. Receiver of SerDes Reference Clocks
The peak value of the differential transmitter output signal or the differential receiver input
signal is defined as the differential peak voltage, V
Since the differential output signal of the transmitter and the differential input signal of the
receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential
transmitter output signal or the differential receiver input signal is defined as differential
peak-to-peak voltage, V
differential swing in amplitude, or twice of the differential peak. For example, the output
differential peak-peak voltage can also be calculated as V
The differential waveform is constructed by subtracting the inverting signal (SD_[A–J]_TX,
for example) from the non-inverting signal (SD_[A–J]_TX, for example) within a differential
pair. There is only one signal trace curve in a differential waveform. The voltage
represented in the differential waveform is not referenced to ground. Refer to
an example for differential waveform.
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes output,
V
the two complimentary output voltages within a differential pair. In a system, the common
mode voltage may often differ from one component’s output to the other’s input. It may be
different between the receiver input and driver output circuits within the same component.
It is also referred to as the DC offset on some occasions.
cm_out
50 Ω
50 Ω
DIFFp-p
= (V
) is 1000 mV p-p.
SD_[A–J]_TX
DIFFp-p
+ V
SD_[A–J]_TX)
= 2 × V
DIFFp
Definition
÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of
Input
Amp
= 2 × |(A – B)| volts, which is twice the
DIFFp
= |X– Y| volts.
TX-DIFFp-p
Electrical Characteristics
= 2 × |V
DIFFp
OD
Figure 2
) is 500 mV.
|.
OD
) has
as
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