AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 96

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-63
The number of DIFF-bits active depends on the configuration depth and width
Figure 2-63 • ALMOST-EMPTY and ALMOST-FULL Logic
Table 2-94 • Number of Available Configuration Bits
2 -8 2
Number of Blocks
1
2
2
4
4
4
8
8
8
8
16
16
16
16
16
Axcelerator Family FPGAs
illustrates flag generation. The Verilog codes for the flags are:
assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0;
assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;
RCLK
WCLK
WCNTR
RCNTR
[15:0]
[15:0]
ALMOST EMPTY and ALMOST FULL Logic
AEVAL [7:0], GND [7:0] (MSB....LSB)
AFVAL [7:0], GND [7:0] (MSB....LSB)
16
16
Block DxW
1x16
16x1
1x1
1x2
2x1
1x4
2x2
4x1
1x8
2x4
4x2
8x1
2x8
4x4
8x2
v2.7
DIFF [15:0]
X
Y
X
Y
(Table
AEMPTY
AFULL
Number of AEVAL/AFVAL Bits
(16 bit)
2-94).
X>=Y
4
4
5
4
5
6
4
5
6
7
4
5
6
7
8