AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 26

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

5V Tolerance
There are two schemes to achieve 5V tolerance:
1. 3.3V PCI and 3.3V PCI-X are the only I/O standards
An external series resister (~100Ω) is required between
the input pin and the 5V signal source to limit the
current
Figure 2-3 • Use of an External Resistor for 5V Tolerance
2. 5V tolerance can also be achieved with 3.3V I/O
Figure 2-4 • Bus Switch IDTQS32X2384
Simultaneous Switching Outputs (SSO)
When multiple output drivers switch simultaneously,
they induce a voltage drop in the chip/package power
distribution. This simultaneous switching momentarily
raises the ground voltage within the device relative to
the system ground. This apparent shift in the ground
potential to a non-zero value is known as simultaneous
switching noise (SSN) or more commonly, ground
bounce.
SSN becomes more of an issue in high pin count
packages and when using high performance devices such
as the Axcelerator family. Based upon testing, Actel
2 -1 2
Axcelerator Family FPGAs
that directly allow 5V tolerance. To implement this,
an internal clamp diode between the input pad and
the V
input pin is clamped as shown in
V
standards (3.3V PCI, 3.3V PCI-X, and LVTTL) using a
bus-switch product (e.g. IDTQS32X2384). This will
convert the 5V signal to a 3.3V signal with minimum
delay
3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.
input
(Figure
Non-Actel Part
CCI
= V
(Figure
CCI
pad is enabled so that the voltage at the
5V
+ V
2-3).
2-4).
diode
5V
5V
= 3.3V + 0.8V = 4.1V
R ext
3.3V
Actel FPGA
clamp
diode
3.3V
20X
3.3V
PCI
EQ
2-3:
3.3V
EQ 2-3
v2.7
recommends that users not exceed eight simultaneous
switching outputs (SSO) per each V
this potential burden on designers, Actel has designed all
of the Axcelerator BGAs
the exception of the CS180, which has an I/O to V
pair ratio of nine to one.
Please refer to the
Signal Integrity
I/O Banks and Compatibility
Since each I/O bank has its own user-assigned input
reference voltage (V
voltage (V
be assigned to the same bank.
Table 2-11
common
Similarly,
common V
Table 2-11 • Compatible I/O Standards for Different V
Table 2-12 • Compatible I/O Standards for Different V
Table 2-13 on page 2-13
combinations of voltages and I/O standards that can be
used together in the same I/O bank. Note that two I/O
standards are compatible if:
V
1.5V
1.25V
1.0V
0.75V
V
3.3V
3.3V
2.5V
2.5V
1.8V
1.5V
Notes:
1. V
2. V
REF
CCI
• Their V
• Their V
1
CCI
CCI
is used for both inputs and outputs
tolerance is ±5%
LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3V
SSTL 3 (Class I and II), LVTTL, PCI, LVPECL
LVCMOS 2.5V, GTL+ 2.5V, LVDS
LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS
LVCMOS 1.8V
LVCMOS 1.5V, HSTL Class I
Table 2-12
CCI
CCI
V
shows the compatible I/O standards for a
Values
Values
REF
), only I/Os with compatible standards can
.
CCI
REF
application note for more information.
values are identical.
standards are identical (if applicable).
Compatible Standards
(for
Simultaneous Switching Noise and
shows compatible standards for a
REF
voltage-referenced
) and an input/output supply
SSTL 3 (Class I and II)
SSTL 2 (Class I and II)
GTL+ (2.5V and 3.3V Outputs)
HSTL (Class I)
3
to not exceed this limit with
Compatible Standards
summarizes the different
CCI
2
/GND pair. To ease
standards).
2
CCI
1.0
1.5
1.0
1.25
N/A
0.75
V
/GND
REF
CCI
REF