AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 53

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Differential Standards
Physical Implementation
Implementing differential I/O standards requires the
configuration of a pair of external I/O pads, resulting in a
single internal signal. To facilitate construction of the
differential pair, a single I/O Cluster contains the
resources for a pair of I/Os. Configuration of the I/O
Cluster as a differential pair is handled by Actel's
Designer software when the user instantiates a
differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
Figure 2-25 • LVDS Board-Level Implementation
The LVDS circuit consists of a differential driver
connected to a terminated receiver through a constant-
impedance transmission line. The receiver is a wide-
common-mode-range
common-mode range is from 0.2V to 2.2V for a
differential input with 400 mV swing.
To implement the driver for the LVDS circuit, drivers from
two adjacent I/O cells are used to generate the
differential signals (note that the driver is not a current-
mode driver). This driver provides a nominal constant
Table 2-55 • DC Input and Output Levels
DC Parameter
V
V
V
V
V
V
1. +/- 5%
2. Differential input voltage =+/-350mV.
CCI
OH
OL
ODIFF
OCM
ICM
1
2
OUTBUF_LVDS
Supply Voltage
Output High Voltage
Output Low Voltage
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
differential
FPGA
N
P
amplifier.
Description
165Ω
165Ω
The
140Ω
v2.7
ZO=50Ω
ZO=50Ω
(OutReg), Enable Register (EnReg), and Double Data
Rate
bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a
high-speed, differential I/O standard. It requires that one
data bit is carried through two signal lines, so two pins
are needed. It also requires an external resistor
termination. The voltage swing between these two
signal lines is approximately 350 mV.
current of 3.5 mA. When this current flows through a
100 Ω termination resistor on the receiver side, a voltage
swing of 350 mV is developed across the resistor. The
direction of the current flow is controlled by the data fed
to the driver.
An external-resistor network (three resistors) is needed
to reduce the voltage swing to about 350 mV. Therefore,
four external resistors are required, three for the driver
and one for the receiver.
(DDR).
100Ω
2.375
1.125
Min.
1.25
250
0.9
0.2
However,
N
P
1.425
1.075
Typ.
1.25
1.25
350
2.5
there
+
–
FPGA
Axcelerator Family FPGAs
is
INBUF_LVDS
Max.
2.625
1.375
1.25
450
1.6
2.2
no
support
Units
mV
V
V
V
V
V
2-39
for