AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 78

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Functional Description
Figure 2-48 on page 2-63
the PLL. The PLL contains two dividers, i and j, that allow
frequency scaling of the clock signal:
Table 2-79 • PLL Interface Signals
2 -6 4
Signal Name
RefCLK
FB
PowerDown
DIVI[5:0]
DIVJ[5:0]
LowFreq
Osc[2:0]
DelayLine[4:0]
FBMuxSel
REFSEL
OUTSEL
Axcelerator Family FPGAs
• The i divider in the feedback path allows
• The j divider divides the PLL output by integer
• The two dividers together can implement any
• The output frequencies of the two clocks are given
f
f
CLK1
CLK2
multiplication of the input clock by integer factors
ranging from 1 to 64, and the resultant frequency
is available at the output of the PLL block.
factors ranging from 1 to 64, and the divided clock
is available at CLK1.
combination of multiplication and division up to a
maximum frequency of 1 GHz on CLK1. Both the
CLK1 and CLK2 outputs have a fixed 50/50 duty
cycle.
by the following formulas (f
clock frequency):
= f
= f
REF
REF
* (DividerI) / (DividerJ)
* (DividerI)
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
User Accessible
illustrates a block diagram of
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
REF
is the reference
(increments), in signed-
Allowable Values
and-magnitude binary
binary notation offset
1 to 64, in unsigned
representation
–15 to +15
by -1
EQ 2-4
EQ 2-5
XX0
001
011
101
111
0
1
0
1
v2.7
The input and output frequency ranges are selected by
LowFreq and Osc(2:0), respectively. These functions and
their possible values are detailed in
The delay lines shown in
programmable. The feedback clock path can be delayed
(using the five DelayLine bits) relative to the reference
clock (or vice versa) by up to 3.75 ns in increments of
250 ps.
delay increments are independent of frequency, so this
results in phase changes that vary with frequency. The
delay value is highly dependent on V
grade.
Figure 2-49 on page 2-65
various control signals to the PLL and shows how the PLL
interfaces with the global and routing networks of the
FPGA. Note that not all signals are user-accessible. These
non-user-accessible signals are used by Actel's place-and-
route tool to control the configuration of the PLL. The
user gains access to these control signals either based
upon the connections built in the user's design or
through the special macros
inserted into the design. For example, connecting the
macro PLLOUT to CLK2 will control the OUTSEL signal.
Reference Clock for the PLL
Feedback port for the PLL
PLL power down control
PLL powered down
PLL active
Sets value for feedback divider (multiplier)
Sets value for CLK1 divider
Input frequency range selector
Output frequency range selector
Clock Delay (positive/negative) in increments of 250 ps, with
maximum value of ± 3.75 ns
Selects the source for the feedback input
Selects the source for the reference clock
Selects the source for the routed net output
• CLK2 provides the PLL output directly—without
50–200 MHz
14–50 MHz
400–1000 MHZ
200–400 MHZ
100–200 MHZ
50–100 MHZ
20–50 MHZ
division
Table 2-79
describes the usage of these bits. The
Function
Figure 2-48 on page 2-63
is a logical diagram of the
(Table 2-83 on page
Table
CC
2-79.
and the speed
2-67)
are