AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 61

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

R-Cell
Introduction
The R-cell, the sequential logic resource of the
Axcelerator devices, is the second logic module type in
the AX family architecture. It includes clock inputs for all
eight global resources of the Axcelerator architecture as
well as global presets and clears
The main features of the R-cell include the following:
Figure 2-31 • R-Cell
• Direct connection to the adjacent logic module
• The R-cell can be used as a standalone flip-flop. It
• Provision of data enable-input (S0).
• Independent active-low asynchronous clear (CLR).
• Independent
through the hardwired connection DCIN. DCIN is
driven by the DCOUT of an adjacent C-cell via the
Direct-Connect routing resource, providing a
connection with less than 0.1 ns of routing delay.
can be driven by any C-cell or I/O modules through
the regular routing structure (using DIN as a
routable data input). This gives the option of
using the R-Cell as a 2:1 MUXed flip-flop as well.
(PSET). If both CLR and PSET are low, CLR has
higher priority.
DIN(user signals)
active-low
Internal Logic
HCLKA/B/C/D
CLKE/F/G/H
(Figure
DCIN
asynchronous
2-31).
preset
v2.7
As with the C-cell, the configuration of the R-cell to
perform various functions is handled automatically for
the user through Actel's extensive macro library (please
see Actel’s
listing of available AX macros).
• Clock can be driven by any of the following (CKP
• Global power-on clear (GCLR) and preset (GPSET),
• S0, S1, PSET, and CLR can be driven by routed
• DIN and S1 can be driven by user signals.
selects clock polarity):
– One of the four high performance hardwired
– One of the four routed clocks (CLKs)
– User signals
which drive each flip-flop on a chip-wide basis.
– When the Global Set Fuse option in the
clocks CLKE/F/G/H or user signals.
fast clocks (HCLKs)
Designer software is unchecked (by default),
GCLR = 0 and GPSET =1 at device power-up.
When the option is checked, GCLR = 1 and
GPSET= 0. Both pins are pulled High when the
device is in user mode.
Antifuse Macro Library Guide
Axcelerator Family FPGAs
for a complete
2-47