AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 84

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Adjustable Clock Delay
Figure 2-55
case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output
clock is accomplished by using the delay line in the feedback path.
Figure 2-55 • Using the PLL Delaying the Reference Clock
2 -7 0
Axcelerator Family FPGAs
PowerDown
FB
illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this
133 MHz
RefCLK
FBMuxSel
Delay Line
Delay Line
DelayLine
5
/i Delay
Match
DividerI
6
÷1
/j
v2.7
LowFreq
PLL
3
Osc
DividerJ
/j Delay
Match
6
/j
133 MHz
Lock
CLK1
CLK2