AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 92

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-91 • Eight RAM Blocks Cascaded
2 -7 8
Parameter
Write Mode
t
t
t
t
t
t
t
t
t
Read Mode
t
t
t
t
t
t
t
t
t
WDASU
WDAHD
WADSU
WADHD
WENSU
WENHD
WCKH
WCLK
WCKP
RADSU
RADHD
RENSU
RENHD
RCK2RD1
RCK2RD2
RCLKH
RCLKL
RCKP
Axcelerator Family FPGAs
Worst-Case Commercial Conditions V
Write Data Setup vs. WCLK
Write Data Hold vs. WCLK
Write Address Setup vs. WCLK
Write Address Hold vs. WCLK
Write Enable Setup vs. WCLK
Write Enable Hold vs. WCLK
WCLK Minimum High Pulse Width
WCLK Minimum Low Pulse Width
WCLK Minimum Period
Read Address Setup vs. RCLK
Read Address Hold vs. RCLK
Read Enable Setup vs. RCLK
Read Enable Hold vs. RCLK
RCLK-To-OUT (Pipelined)
RCLK-To-OUT (Non-Pipelined)
RCLK Minimum High Pulse Width
RCLK Minimum Low Pulse Width
RCLK Minimum Period
Description
CCA
= 1.425V, V
v2.7
13.35
15.02
Min.
0.98
6.68
0.95
7.51
CCI
'–2' Speed
= 3.0V, T
Max.
5.78
5.78
5.78
6.75
6.75
0.00
3.57
5.48
0.22
0.22
0.22
0.00
J
= 70°C
15.21
17.11
Min.
1.11
1.08
8.55
7.6
'–1' Speed
Max.
6.58
0.25
6.58
0.25
6.58
0.25
7.69
0.00
7.69
0.00
4.06
6.24
17.88
10.05
20.11
Min.
1.31
8.94
1.27
'Std' Speed
Max.
7.74
7.74
7.74
9.04
0.00
9.04
0.00
4.77
7.34
0.3
0.3
0.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns