AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 47
AX500-1BG896
Manufacturer Part Number
AX500-1BG896
Description
Axcelerator Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.AX500-1BG896.pdf
(226 pages)
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Table 2-39 • 3.3V GTL+ I/O Module
Parameter
3.3V GTL+I/O Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DP
PY
ICLKQ
OCLKQ
SUD
SUE
HD
HE
CPWHL
CPWLH
WASYN
REASYN
HASYN
CLR
PRESET
Worst-Case Commercial Conditions V
Input Buffer
Output Buffer
Clock-to-Q for the I/O input register
Clock-to-Q for the IO output register and the I/O
enable register
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Description
CCA
= 1.425V, V
v2.7
CCI
= 3.0V, T
Min.
0.43
0.45
0.43
'–2' Speed
Max.
1.75
1.01
0.67
0.67
0.23
0.26
0.00
0.00
0.10
0.00
0.23
0.23
J
= 70°C
Min.
0.48
0.51
0.48
'–1' Speed
Max.
1.99
1.15
0.77
0.77
0.27
0.30
0.00
0.00
0.10
0.00
0.27
0.27
Axcelerator Family FPGAs
Min.
'Std' Speed
0.57
0.60
0.57
Max.
0.31
0.35
0.00
0.00
0.10
0.00
0.31
2.35
1.36
0.90
0.90
0.31
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-33
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