AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 77

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Axcelerator Clock Management System
Introduction
Each member of the Axcelerator family contains eight
phase-locked loop (PLL) blocks which perform the
following functions:
Each PLL has the following key features:
Physical Implementation
The eight PLL blocks are arranged in two groups of four.
One group is located in the center of the northern edge
of the chip, while the second group is centered on the
Figure 2-48 • PLL Block Diagram
• Programmable Delay (32 steps of 250 ps)
• Clock Skew Minimization
• Clock Frequency Synthesis
• Input Frequency Range – 14 to 200 MHz
• Output Frequency Range – 20 MHz to 1 GHz
• Output Duty Cycle Range – 45% to 55%
• Maximum Long-Term Jitter – 1% or 100ps
• Maximum Short-Term Jitter – 50ps + 1% of Output
• Maximum Acquisition Time (lock) – 20µs
(whichever is greater)
Frequency
PowerDown
FB
RefCLK
FBMuxSel
Delay Line
Delay Line
DelayLine
5
/i Delay
Match
DIVJ
6
/i
LowFreq
v2.7
PLL
southern edge. The northern group is associated with
the four HCLK networks (e.g. PLLA can drive HCLKA),
while the southern group is associated with the four CLK
networks (e.g. PLLE can drive CLKE).
Each PLL cell is connected to two I/O pads and a PLL
Cluster that interfaces with the FPGA core.
illustrates a PLL block. The V
connected to a 1.5V power supply through a 250 Ω
resistor. Furthermore, 0.1 μF and 10 μF decoupling
capacitors should be connected across the V
V
grounded
The I/O pads associated with the PLL can also be
configured for regular I/O functions except when it is
used as a clock buffer. The I/O pads can be configured in
all the modes available to the regular I/O pads in the
same I/O bank. In particular, the [H]CLKxP pad can be
configured as a differential pair, single-ended, or
voltage-referenced standard. The [H]CLKxN pad can only
be used as a differential pair with [H]CLKxP.
The block marked “/i Delay Match” is a fixed delay equal
to that of the i divider. The “/j Delay Match” block has
the same function as its j divider counterpart.
COMPPLL
3
Osc
pins. Note: The V
(Figure 2-2 on page
/j Delay
Match
DIVJ
6
/j
COMPPLL
2-9)!
Axcelerator Family FPGAs
CCPLL
pin should never be
pin should be
Lock
CLK1
CLK2
Figure 2-48
CCPLL
and
2-63