AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 88

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Modes of Operation
There are two read modes and one write mode:
In the standard read mode, new data is driven onto the
RD bus in the clock cycle immediately following RA and
REN valid. The read address is registered on the read-
port active-clock edge and data appears at read-data
after the RAM access time. Setting the PIPE to OFF
enables this mode.
The pipelined mode incurs an additional clock delay
from address to data, but enables operation at a much
Timing Characteristics
Figure 2-58 • SRAM Model
Figure 2-59 • RAM Write Timing Waveforms
2 -7 4
Axcelerator Family FPGAs
• Read Nonpipelined (synchronous – one clock edge)
• Read Pipelined (synchronous – two clock edges)
• Write (synchronous – one clock edge)
WCLK
WCLK
WEN
t
WD
WA
WCKP
WA<11:0>, WD<35:0>, WEN<4:0>
v2.7
t
WCKH
higher frequency. The read-address is registered on the
read-port active-clock edge, and the read data is
registered and appears at RD after the second read clock
edge. Setting the PIPE to ON enables this mode.
On the write active-clock edge, the write data are
written into the SRAM at the write address when WEN is
high. The setup time of the write address, write enables,
and write data are minimal with respect to the write
clock.
Write and read transfers are described with timing
requirements beginning in
t
WCKL
RA
RD
RCLK
REN
t
WxxSU
"Timing
t
WxxHD
Characteristics".