AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 82

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

User Flow
There are two methods of including a PLL in a design:
Note: t
Figure 2-52 • PLL Model
2 -6 8
Timing Model
Axcelerator Family FPGAs
•
create custom PLL blocks using Actel's macro
generator, SmartGen, that can be instantiated in a
design.
PCLK
The recommended method of using a PLL is to
is the delay in the clock signal
CLK
FB
t
PCLK
*
6
v2.7
6
5
• The alternative method is to instantiate one of the
generic library primitives (PLL or PLLFB) into either
a schematic or HDL netlist, using inverters for
polarity control and tying all unused address and
data bits to ground.
3
Lock
CLK1
CLK2