ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 70

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Pin Information
In Table 31, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out
of the embedded core.
Table 31. Embedded Core/FPGA Interface Signal Description
70
STM or 8B/10B Signals
doutaa<7:0>
doutab<7:0>
doutaa_c1j1
doutab_c1j1
doutaa_spe
doutab_spe
dinaa<7:0>
dinab<7:0>
dinad<7:0>
dinba<7:0>
dinbb<7:0>
dinbd<7:0>
doutaa_par
doutab_par
dinac<7:0>
dinbc<7:0>
doutaa_en
doutab_en
Pin Name
dinaa_par
dinab_par
dinac_par
dinad_par
dinba_par
dinbb_par
dinbc_par
dinbd_par
doutaa_fp
doutab_fp
dinaa_fp
dinab_fp
dinac_fp
dinad_fp
dinba_fp
dinbb_fp
dinbc_fp
dinbd_fp
(continued)
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Parallel bus of STM slice A, transmitter A. MSB is bit 7.
Parity for STM slice A, transmitter A.
Frame pulse or K control for STM slice A, transmitter A.
Parallel bus of STM slice A, transmitter B. MSB is bit 7.
Parity for STM slice A, transmitter B.
Frame pulse or K control for STM slice A, transmitter B.
Parallel bus of STM slice A, transmitter C. MSB is bit 7.
Parity for STM slice A, transmitter C.
Frame pulse or K control for STM slice A, transmitter C.
Parallel bus of STM slice A, transmitter D. MSB is bit 7.
Parity for STM slice A, transmitter D.
Frame pulse or K control for STM slice A, transmitter D.
Parallel bus of STM slice B, transmitter A. MSB is bit 7.
Parity for STM slice B, transmitter A.
Frame pulse or K control for STM slice B, transmitter A.
Parallel bus of STM slice B, transmitter B. MSB is bit 7.
Parity for STM slice B, transmitter B.
Frame pulse or K control for STM slice B, transmitter B.
Parallel bus of STM slice B, transmitter C. MSB is bit 7.
Parity for STM slice B, transmitter C.
Frame pulse or K control for STM slice B, transmitter C.
Parallel bus of STM slice B, transmitter D. MSB is bit 7.
Parity for STM slice B, transmitter D.
Frame pulse or K control for STM slice B, transmitter D.
Parallel bus of STM slice A, receiver A. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver A.
SPE signal for parallel bus of STM slice A, receiver A.
C1J1 signal for parallel bus of STM slice A, receiver A.
Enable for parallel bus of STM slice A, receiver A.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver A.
Parallel bus of STM slice A, receiver B. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver B.
SPE signal for parallel bus of STM slice A, receiver B.
C1J1 signal for parallel bus of STM slice A, receiver B.
Enable for parallel bus of STM slice A, receiver B.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver B.
Description
Agere Systems Inc.
August 2001
Data Sheet