ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 66

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Pin Information
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary.
Table 30. FPSC Function Pin Description
* The V
66
HSI LVDS Receive Pins
SS
V
V
DAUTREC
rxd_b_p0
rxd_b_n0
rxd_c_p0
rxd_c_n0
rxd_b_p1
rxd_b_n1
rxd_c_p1
rxd_c_n1
rxd_b_p2
rxd_b_n2
rxd_c_p2
rxd_c_n2
rxd_b_p3
rxd_b_n3
rxd_c_p3
rxd_c_n3
rxd_b_p4
rxd_b_n4
rxd_c_p4
rxd_c_n4
rxd_b_p5
rxd_b_n5
rxd_c_p5
rxd_c_n5
rxd_b_p6
rxd_b_n6
rxd_c_p6
rxd_c_n6
rxd_b_p7
rxd_b_n7
rxd_c_p7
rxd_c_n7
SSA
A_STM is combimed with V
DDA
Symbol
_STM*
_STM
(continued)
I/O
SS
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
in packages that contain an internal V
LVDS work link—channel AA (shared with RapidIO port B) .
LVDS work link—channel AA (shared with RapidIO port B).
LVDS protect link—channel AA (shared with RapidIO port C).
LVDS protect link—channel AA (shared with RapidIO port C).
LVDS work link—channel AB (shared with RapidIO port B).
LVDS work link—channel AB (shared with RapidIO port B).
LVDS protect link—channel AB (shared with RapidIO port C).
LVDS protect link—channel AB (shared with RapidIO port C).
LVDS work link—channel AC (shared with RapidIO port B).
LVDS work link—channel AC (shared with RapidIO port B).
LVDS protect link—channel AC (shared with RapidIO port C).
LVDS protect link—channel AC (shared with RapidIO port C).
LVDS work link—channel AD (shared with RapidIO port B).
LVDS work link—channel AD (shared with RapidIO port B).
LVDS protect link—channel AD (shared with RapidIO port C).
LVDS protect link—channel AD (shared with RapidIO port C).
LVDS work link—channel BA (shared with RapidIO port B).
LVDS work link—channel BA (shared with RapidIO port B).
LVDS protect link—channel BA (shared with RapidIO port C).
LVDS protect link—channel BA (shared with RapidIO port C).
LVDS work link—channel BB (shared with RapidIO port B).
LVDS work link—channel BB (shared with RapidIO port B).
LVDS protect link—channel BB (shared with RapidIO port C).
LVDS protect link—channel BB (shared with RapidIO port C).
LVDS work link—channel BC (shared with RapidIO port B).
LVDS work link—channel BC (shared with RapidIO port B).
LVDS protect link—channel BC (shared with RapidIO port C).
LVDS protect link—channel BC (shared with RapidIO port C).
LVDS work link—channel BD (shared with RapidIO port B).
LVDS work link—channel BD (shared with RapidIO port B).
LVDS protect link—channel BD (shared with RapidIO port C).
LVDS protect link—channel BD (shared with RapidIO port C).
Disable auto recovery for the PLL. Internal pull-down.
Analog V
Analog V
DD
SS
for the HSI block.
1.5 V power supply for the HSI block.
SS
plane.
Description
Agere Systems Inc.
August 2001
Data Sheet