ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 12

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850 Overview
Device Layout
The ORT8850 FPSC provides a high-speed backplane
transceiver combined with FPGA logic. The device is
based on 1.5 V OR4E2 or OR4E6 FPGAs. The OR4E2
has a 26 x 24 array of programmable logic cells (PLCs)
and the OR4E6 has a 46 x 44 array. For the ORT8850,
several columns of PLCs in these arrays were replaced
with the embedded backplane transceiver core.
The ORT8850 embedded core comprises a long-haul
interface macro and three RapidIO macros for intra-
board chip-to-chip or backplane communication. The
long-haul interface includes the high-speed interface
(HSI) macrocell, the synchronous transport module
(STM) macrocell, and a 8B/10B encoder/decoder. The
eight full-duplex channels perform data transfer, scram-
bling/descrambling or encoding/decoding, and framing
at the rate of 850 Mbits/s. Each RapidIO block has a
transmit and receive section that each contain one
LVDS clock buffer pair, one LVDS start-of-cell buffer
pair, and eight LVDS clock buffer pairs which are dou-
ble edge clocked by the corresponding clock. Figure 1
shows the ORT8850 block diagram.
Backplane Transceiver Interface
The advantage of the ORT8850 FPSC is to bring spe-
cific networking functions to an early market presence
using programmable logic in a system.
The 850 Mbits/s backplane transceiver core allows the
ORT8850 to communicate across a backplane or on a
given board at an aggregate speed of 6.8 Gbits/s, pro-
viding a physical medium for high-speed asynchronous
serial data transfer between system devices. This
device is intended for, but not limited to, connecting ter-
minal equipment in SONET/SDH, ATM, and IP sys-
tems.
The backplane transceiver core is used to support a
6.8 Gbits/s interface for backplane connection to a
mate TADM042G5 device or other SONET devices
such as redundant central crossconnect. The interface
is implemented as an eight-channel 850 Mbits/s LVDS
12
12
links. The HSI macrocell is used for clock/data recov-
ery (CDR) and serialize/deserialize between the
106.25 MHz byte-wide internal data buses and the
850 Mbits/s serial LVDS links. For a 622 Mbits/s
SONET stream, the HSI will perform clock and data
recovery (CDR) and MUX/deMUX between 77.76 MHz
byte-wide internal data buses and 622 Mbits/s serial
LVDS links.
Each 850 Mbits/s serial link uses a pseudo-SONET
protocol. SONET A1/A2 framing is used on the link to
detect the 8 kHz frame location. The link is also scram-
bled using the standard SONET scrambler definition to
ensure proper transitions on the link for improved CDR
performance. Selectable transport overhead (TOH)
bytes are insertable in the transmit direction. All the
selectable bytes are inserted from software program-
mable registers that are accessed via a microproces-
sor interface.
Elastic buffers (FIFOs) are used to align each incoming
STS-12 link to the 77.76 MHz clock and 8 kHz frame.
These FIFOs will absorb delay variations between the
four 622 Mbits/s links due to timing skews between
cards and along backplane traces. For greater varia-
tions, a streamlined pointer processor (pointer mover)
within the STM macro will align the 8 kHz frames
regardless of their incoming frame position.
The backplane transceiver allows for SONET scram-
bling and frame alignment or 8-bit/10-bit (8B/10B)
encoding/decoding. SONET has the advantage of
reduced overhead (3.3% overhead for SONET vs. 25%
overhead for 8B/10B). 8B/10B has the advantage of
faster synchronization (a few bytes of transferred data
for 8B/10B vs. up to 500 s for four frames of data for
SONET). The effective data transfer rate for scrambled
SONET is greater than 800 Mbits/s while the effective
data transfer rate for 8B/10B is greater than
680 Mbits/s. Frame synchronization and multichannel
alignment is provided in 8B/10B mode through the use
of special K characters.
Figure 2 shows the architecture of the ORT8850 back-
plane transceiver core.
Agere Systems Inc.
August 2001
Data Sheet