ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 65

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Pin Information
Table 29. FPGA Common-Function Pin Description (continued)
* The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
MPI_TSZ[1:0]
MPI_BURST
MPI_RTRY
MPI_BDIP
MPI_ACK
MPI_CLK
MPI_TEA
Symbol
DP[3:0]
D[0:31]
A[0:17]
DOUT
DIN
I/O
I/O Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transac-
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O After configuration, DOUT is a user-programmable I/O pin.*
O During master parallel configuration mode, A[0:17] address the configuration EPROM. In
O In PowerPC mode MPI operation, this is driven low indicating the MPI received the data
O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
O This pin requests that the MPC860 relinquish the bus and retry the cycle.
O During configuration, DOUT is the serial data output that can drive the DIN of daisy-
I
I
I
I
(continued)
During slave serial or master serial configuration modes, DIN accepts serial configuration
During MPI mode, the A[0:17] are used as the address bus driven by the PowerPC bus
master, utilizing the least significant bits of the PowerPC 32-bit address.
MPI mode, many of the A[n] pins have alternate uses as described below. See the special
function blocks section for more MPI information. During configuration, if not in master
parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.
It is driven low to indicate a burst transfer is in progress. Driven high indicates that the
current transfer is not a burst.
It is driven by the PowerPC processor assertion of this pin indicates that the second beat
in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size
for the transaction. Set 10 for byte, 01 for half-word, and 00 for word.
If not used for MPI, these pins are user-programmable I/O pins.*
on the write cycle or returned data on a read cycle.
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It
can be a source of the clock for the embedded system bus. If MPI is used, this can be the
AMBA bus clock.
the internal system bus for the current transaction.
tion. Driven by MPI in a read transaction.
D[0:7] receive configuration data during master parallel, peripheral, and slave parallel
configuration modes and each pin has a pull-up enabled. During serial configuration
modes, D0 is the DIN input.
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
After configuration, the pins are user-programmable I/O pins.*
D[16:23], and DP[3] for D[24:32].
After configuration, this pin is a user-programmable I/O pin.*
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.
During configuration, a pull-up is enabled.
chained slave devices. Data out on DOUT changes on the rising edge of CCLK.
Eight-Channel x 850 Mbits/s Backplane Transceiver
Description
ORCA ORT8850 FPSC
65