ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 42

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Memory Map
Table 11. Memory Map (continued)
* The FIFO aligner threshold error flag is only valid if a FIFO out of sync error flag is also present.
42
24, 3c,
54, 6c,
84, 9c,
25, 3d,
55, 6d,
85, 9d,
26, 3e,
56, 6e,
86, 9e,
28, 40,
58, 70,
88, a0,
29, 41,
59, 71,
ADDR
b5, cd
b6, ce
27, 3f,
57, 6f,
87, 9f,
b8, d0
89, a1
b9, d1
b4, cc
b7, cf
[7:0]
Register
Type
isreg
iereg
iareg
iereg
sreg
sreg
indication
Concat
(continued)
DB7
11
—
—
—
—
—
indication
error flag
Concat
(Out of
Sync)
FIFO
DB6
—
—
—
—
8
indication
input port
error flag
Concat
serial
parity
TOH
DB5
—
—
—
5
indication
bus parity
error flag
parallel
Concat
input
DB4
—
—
—
2
enable/mask register [0:5]
LVDS link
indication
indication
B1 parity
error flag
Concat
Concat
DB3
12
10
—
—
indication
indication
overflow
LOF flag
Concat
Concat
elastic
store
DB2
flag
enable/mask register [0:3]
9
7
indication
indication
ais-p flag
error flag
Receiver
internal
Concat
Concat
parity
DB1
path
6
4
per sts-12
alarm flag
indication
indication
threshold
error flag
Concat
Concat
aligner
FIFO*
MSB
DB0
3
1
Agere Systems Inc.
Reset
Value
[7:0]
NA
NA
00
00
00
00
August 2001
Data Sheet
Comment