ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 53

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Memory Map
Table 12. Memory Map Descriptions (continued)
LVDS link b1 parity error
counter
LOF counter
A1 A2 frame error counter 34, 4c, 64,
FIFO depth register
Sampler phase error
counter
Bypass register
Bypass register
Enable work/protect chan-
nels
Sync control register
Disable framer
Bit/Register Name(S)
(continued)
32, 4a, 62,
7a, 92, aa,
33, 4b, 63,
7b, 93, ab,
35, 4d, 65,
7d, 95, ad,
36, 4e, 66,
7e, 96, ae,
7c, 94, ac,
37, 4f, 67,
37, 4f, 67,
37, 4f, 67,
c7, df[3:4]
37, 4f, 67,
Location
67,7f, 97,
7f, 97, af,
7f, 97, af,
7f, 97, af,
7f, 97, af,
Register
c7, df[1]
c7, df[2]
c7, df[5]
b2, da
b3, db
b4, dc
c5, dd
c6, de
37, 4f,
af, c7,
(Hex)
[0:7]
[0:7]
[0:7]
[3:7]
[0:7]
df[0]
Bit/
Register
counter
counter
counter
counter
Type
sreg
creg
creg
creg
creg
creg
Eight-Channel x 850 Mbits/s Backplane Transceiver
Reset
Value
(Hex)
00
00
00
30
00
00
0
0
0
0
7 bit count + overflow – reset on read.
7 bit count + overflow – reset on read increments on
a change from in-frame to out-of-frame state.
7 bit count + overflow – reset on read.
30 indicates FIFO is half full.
Write 1 to clear.
1: Bypass pointer mover.
1: Bypass alignment FIFO + pointer mover.
Bit to control the LVDS drivers/receivers to/from
CDR.
0: Use LVDS drivers and receivers to/from Pi-sched
I/F block B (work channels).
1: Use LVDS drivers and receivers to/from Pi-sched
I/F block C (protect channels).
00: No alignment.
01: Align with twin (i.e., STM B stream A).
10: Align with all 4 (i.e., STM A all streams).
11: Align with all 8 (i.e., STM A and B all streams).
0: Enable framer.
1: Disable STS-12 framing.
Description
ORCA ORT8850 FPSC
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