ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 29

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Backplane Transceiver Core Detailed
Description
The FIFO block consists of a 24-bit by 10-bit FIFO per
link. This FIFO is used to align up to ±154.3 ns of inter-
link skew and to transfer to the system clock. The FIFO
sync circuit takes metastable hardened frame pulses
from the write control blocks and produces sync signals
that indicate when the read control blocks should begin
reading from the first FIFO location. On top of the sync
signals, this block produces an error indicator which
indicates that the signals to be aligned are too far apart
for alignment (i.e., greater than 18 clocks apart). Sync
and error signals are sent to read control block for
alignment. The read control block is synched only once
on start-up; any further synchronization is software
controlled. The action of resynching a read control
block will always cause loss of data. A register allows
the read control block to be resynched.
STM Link Alignment
The general operation of the link alignment algorithm is
to wait 12 clocks (i.e., half the FIFO) from the arriving
frame pulse and then signal the read control block to
begin reading. For perfectly aligned frame pulses
across the links, it is simply a matter of counting down
12 and then signaling the read control block.
The algorithm down counts by one until all of the frame
pulses have arrived and then by two when they are all
present. For example (Figure 12), if all pulses arrive
together, then alignment algorithm would count 24
(12 clocks); if, however, the arriving pulses are spread
out over four clocks, then it would count one for the first
four pulses and then two per clock afterward, which
gives a total of 14 clocks between first frame pulse and
the first read. This puts the center of arriving frame
pulses at the halfway point in the buffer. This is the
extent of the algorithm, and it has no facility for actively
correcting problems once they occur.
The write control block receives byte-wide data at
77.76 MHz and a frame pulse two clocks before the
first A1 byte of the STS-12 frame. It generates the write
Agere Systems Inc.
TO G E TH E R
(W R ITIN G
B E G IN S )
A LL FP s
A R R IV E
(continued)
P E R FE C TLY A LIG N E D FR A M E S
12 C LO C K S
24-byte
FIFO
Figure 12. Examples of Link Alignment
S Y N C . P U LS E
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Eight-Channel x 850 Mbits/s Backplane Transceiver
address for the FIFO block. The first A1 in every STS-
12 stream is written in the same location (address 0) in
the FIFO. Also, a frame bit is passed through the FIFO
along with the first byte before the first A1 of the STS-
12. The read control block synchronizes the reading of
the FIFO for streams that are to be aligned. Reading
begins when the FIFO sync signals that all of the appli-
cable A1s and the appropriate margin have been writ-
ten to the FIFO. All of the read blocks to be
synchronized begin reading at the same time and
same location in memory (address 0).
The alignment algorithm takes the difference between
read address and write address to indicate the relative
clock alignments between STS-12 streams. If this
depth indication exceeds certain limits (12 clocks),
then an interrupt is given to the microprocessor (align-
ment overflow). Each STS-12 stream can be realigned
by software if it gets too far out of line (this would
cause a loss of data). For background applications that
have less than 154.3 ns of interlink skew, misalignment
will not occur.
STM Link Alignment Setup
In order to ensure proper operation of the STM Link
Alignment capability, the following setup procedures
should be followed after the enabled channels have a
valid frame pulse:
1. Put all of the streams to be aligned, including dis-
2. Force AIS-L in all streams to be synchronized
3. Wait four frames. Write a 0x01 to the FIFO align-
4. Release the AIS-L in all streams (write 0x00 to
(W R ITIN G
FIR S T FP
A R R IV E S
A R R IV E S
4 C LO C K S
B E G IN S )
LA S T FP
abled streams, into their required alignment mode.
(refer to register map, write 0x01 to DB6 or register
0x30020, 0x30038, 0x30050, 0x30068, 0x30080,
0x30098, 0x300B0, and 0x300C8).
ment resync register bits as required in register
0x30017 or 0x30018. Wait four frames.
DB6 or register 0x30020, 0x30038, 0x30050,
0x30068, 0x30080, 0x30098, 0x300B0, and
0x300C8). This procedure allows normal data flow
through the embedded core.
4-B Y TE S P R E A D IN A R R IV IN G FR A M E S
10 C LO C K S
24-byte
FIFO
ORCA ORT8850 FPSC
S Y N C P U LS E
(R E A D IN G
B E G IN S )
5-8584 (F)
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