ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 34

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed
Description
LVDS Protection Switching
Each SERDES link sends and receives data on two
LVDS buffers. For example, data is transmitted through
SERDES AA to tx_b[0] as the work link and tx_c[0] as
the protect link. Data is received through two LVDS
buffers and a switch is provided to select between the
work and protect buffer. The signal lvds_prot_aa pro-
vided in the FPGA logic selects between the work link
buffer (rx_b[0]) and the protect link buffer (rx_c[0]).
These signals select the protect link when high and the
work link when low.
LVDS protection switching can be used in either 8B/
10B mode or when using STM. STM redundancy and
protection switching discussed in the previous section
can only be used with the STM. LVDS protection
switching can also be switched using software control.
Consult the memory map in Table 10 for more informa-
tion.
RapidIO Interface to Pi-Sched
Overview
The ORT8850 includes three byte-wide, full-duplex
DDR RapidIO interfaces running at up to 311 MHz
(622 Mbits/s) per line for a total of 5.0 Gbits/s for each
interface. Each input and output interface includes
byte-wide data, one control signal (such as start-of-
cell), and one clock signal. One of the three RapidIO
interfaces is always available. The other two RapidIO
interface are available only if the eight CDR channels
are not being used.
One function of the ORT8850 is to interface with the
protocol independent scheduler (Pi-Sched) device on a
port card. The Pi-Sched IC is part of the high-speed
switching (HSSW) family of devices. It offers a highly
integrated, innovative, and complete VLSI solution for
implementing the scheduling and buffer management
functionality of a cell (e.g., ATM) or packet (e.g., IP)
switching system port at OC-48c.
The RapidIO in the ORT8850 will support the dedi-
cated receive and transmit interfaces for off-chip com-
munication. Both interfaces drive or receive off-chip
through LVDS I/O pads. The LVDS I/Os are fully termi-
nated on-chip to allow for driving high-speed parallel
backplanes at speeds up to 311 MHz. Internally, each
8-bit RapidIO interface is connected to a 32-bit inter-
face which is single-edge clocked and connected to the
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FPGA logic array. For example, byte-wide 311 MHz
DDR data is converted to 155 MHz 32-bit wide data at
the FPGA interface.
The primary task of the RapidIO is to process bytes of
data known as octets transmitted as a group known as
a cell. An octet is described as 8 bits found within a
cell. Once the first octet of a cell is received, subse-
quent octets are part of an uninterrupted data stream
until the entire cell has been received. The beginning of
the next cell will determine the boundary of the previ-
ous cell. The beginning of a cell is indicated by a pulse
on the start-of-cell, SOC signal. The SOC signal
always accompanies the cell data. At the I/O boundary,
cell data is present on an 8-bit data bus with the first
octet and SOC aligned with the rising edge of the clock.
At the FPGA end, cell data is present on a 32-bit data
bus. Thus, the RapidIO is used to translate between
the 32-bit data bus and the 8-bit I/O data bus while
monitoring the integrity of the cells being processed.
Receive Cell Interface
The receive interface performs demultiplexing from
four sequential octets of eight pairs of LVDS pins using
both edges of the high-speed clock onto internal 32-bit
buses at the low-speed clock. The interface includes
the following signals (see Figure 14):
The eight LVDS data pairs are double-edge clocked by
the LVDS receive clock (RXCLK). The RXCLK is
aligned to the center of the eye of the received data
and start-of-cell (RXD and RXSOC). To achieve opti-
mal timing margin, the receiver is required to maintain
this alignment. The RapidIO interface requires that the
SOC spacing is an integer multiple of two clock cycles
for proper operation and that SOCs occur only on the
rising edge of the receive clock (RXCLK).
One LVDS clock pair running at 120 MHz—311 MHz.
Its relationship is intended to be in the eye of the
receive cell data.
One LVDS start-of-cell pair, which indicates that
word 0 of a data cell is on the receive data port.
Eight LVDS data pairs, double-edge clocked by the
LVDS clock.
Agere Systems Inc.
August 2001
Data Sheet