ORT8850H AGERE [Agere Systems], ORT8850H Datasheet
ORT8850H
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ORT8850H Summary of contents
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... Columns ORT8850L 26 24 ORT8850H 46 44 Note: The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU) ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Contents Introduction..................................................................1 Embedded Core Features (Serial)...............................4 Embedded Core Features (Parallel)............................4 Programmable FPGA Features ...................................5 Programmable Logic System Features .......................6 Description...................................................................7 What Is an FPSC? ...................................................7 FPSC Overview .......................................................7 FPSC Gate Counting ...
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... Table 28. . LVDS Operating Parameters ....................60 Table 29. . FPGA Common-Function Pin Description ........................................................63 Table 30. . FPSC Function Pin Description ................66 Table 31. . Embedded Core/FPGA Interface Signal Description ....................................................70 Table 32. . ORT8850H Pins That Are Unused in ORT8850L ...............................................................77 Table 33. . ORT8850L 352-Pin PBGA Pinout .............78 Table 34. . ORT8850L and ORT8850H 680-Pin PBGAM Pinout ...........................................88 Table 35. . ORCA ORT8850 Plastic Package Thermal Guidelines ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Embedded Core Features (Serial) Implemented in an ORCA Series 4 FPGA. Allows wide range of applications for SONET net- work termination application as well as generic data moving for high-speed backplane ...
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Data Sheet August 2001 Programmable FPGA Features High-performance platform design: — 0.13 µm 7-level metal technology. — Internal performance of >250 MHz. — Over 600K usable system gates. — Meets multiple I/O interface standards. — 1.5 V operation (30% less ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Programmable FPGA Features Built-in testability: — Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). — Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. — TS_ALL testability ...
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Data Sheet August 2001 Description What Is an FPSC? FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Description (continued) Following design entry, the development system’s map, place, and route tools translate the netlist into a routed FPGA. A floorplanner is available for layout feedback and control. A static ...
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Data Sheet August 2001 Description (continued) The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3- state, bidirectional buffers, and logic to perform 10-bit AND function for decoding, ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver System-Level Features The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block RAMs, univer- sal programmable phase-locked loops, and the addi- tion ...
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Data Sheet August 2001 System-Level Features (continued) Configuration The FPGAs functionality is determined by internal con- figuration RAM. The FPGAs internal initialization/con- figuration circuitry loads the configuration data at powerup or under system control. The configuration data can reside externally ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver ORT8850 Overview Device Layout The ORT8850 FPSC provides a high-speed backplane transceiver combined with FPGA logic. The device is based on 1.5 V OR4E2 or OR4E6 FPGAs. The OR4E2 has a ...
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Data Sheet August 2001 ORT8850 Overview (continued) 850 Mbits/s DATA 8 FULL- DUPLEX LVDS SERIAL I/Os CHANNELS 850 Mbits/s DATA Agere Systems Inc. Eight-Channel x 850 Mbits/s Backplane Transceiver 8-bit/10-bit DECODER PSEUDO- SONET FRAMER BYTE- CLOCK/DATA WIDE RECOVERY POINTER MOVER ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver ORT8850 Overview (continued TER TEM ( ...
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Data Sheet August 2001 ORT8850 Overview (continued) HSI Interface The high-speed interconnect (HSI) macrocell is used for clock/data recovery and MUX/deMUX between 106.25 MHz byte-wide internal data buses and 850 Mbits/s external serial links. The HSI interface receives eight 850 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver ORT8850 Overview (continued) FPSC Configuration Configuration of the ORT8850 occurs in two stages: FPGA bit stream configuration and embedded core setup. FPGA Configuration Prior to becoming operational, the FPGA goes through ...
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Data Sheet August 2001 Generic Backplane Transceiver Application Synchronous Transfer Mode (STM) The combination of ORT8850 and soft IP cores pro- vides a generic data moving solution for non-SONET applications. There is no requirement for SONET knowledge to the users. ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Generic Backplane Transceiver Application PARALLEL FIFO DINXX DATAIN ERROR FLAG PARALLEL DATA OUT DOUTXX SYS_CLK COMMA _DET DOUTXX_FP Figure 3. 8850 with 8B/10B Coding/Decoding Backplane Transceiver Core Detailed Description HSI Macro ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description Rx TSTCLK CREG BYPASS CREG LOOPBKEN LOOPBKCH[(n – 1):0] DIN[(n – 1):0] 848 Mbits/s or 424 Mbits/s or 212 Mbits/s DATA SYSCLK 106 MHz or 85 MHz Tx DOUT[(n –1):0] 848 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) STM Transmitter (FPGA Backplane) The synchronous transport module (STM) portion of the embedded core consists of two slices: STM A and B. Each STM slice ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) Transport Overhead for In-Band Communication The TOH byte can be used for in-band configuration, service, and management since it is carried along the same channel as data. In ORT8850, in-band ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description Table 2. Transmitter TOH on LVDS Output (Transparent Mode ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) B1 Calculation and Insertion In a bit interleaved parity -8 (BIP-8) error check set for even parity over all the bits of an STS-1 frame B1 is defined for the ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) Framer Block The framer block takes byte-wide data from the HSI, and outputs a byte-aligned, byte-wide data stream and 8 kHz sync pulse. The framer ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description Transport Overhead Extraction Transport overhead is extracted from the receive data stream by the TOH extract block. The incoming data gets loaded into a 36-byte shift register on the system clock ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description SPE and C1J1 Outputs. These two signals for each channel are passed to the FPGA logic to allow a pointer pro- cessor or other function to ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description STS- ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) STS-12 STREAM AA STS-12 STREAM AB STM SLICE A STS-12 STREAM AC STS-12 STREAM AD STS-12 STREAM BA STS-12 STREAM BB STM SLICE B STS-12 ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) The FIFO block consists of a 24-bit by 10-bit FIFO per link. This FIFO is used to align up to ±154 inter- link skew and to transfer to ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description 8B/10B Transmitter (FPGA For each channel, an 8B/10B encoder can be enabled in place of the STM transmitter. This block receives 8-bit data from the FPGA ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description 8B/10B Link Alignment Setup In order to align the receive channels in 8B/10B mode, the following procedure should be followed: 1. Enable 8B/10B mode for all eight channels by setting the ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) Pointer Interpreter State Machine. The pointer inter- preter’s highest priority is to maintain accurate data flow (i.e., valid SPE only) into the elastic store. This ...
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Data Sheet August 2001 Backplane Transceiver Core Detailed Description (continued) Receive Bypass Options and FPGA Interface Not all of the blocks in the receive direction are required to be used. The following bypass options are valid in the receive (backplane ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Backplane Transceiver Core Detailed Description (continued) LVDS Protection Switching Each SERDES link sends and receives data on two LVDS buffers. For example, data is transmitted through SERDES AA to tx_b[0] as ...
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Data Sheet August 2001 RapidIO Interface to Pi-Sched 266 MHz CLOCK DOMAIN INPUT DATA CAPTURE D RXD[0] D RXD[7] RXSOC RXCLK Octets and Start of Cell Cells will be transmitted on the high-speed LVDS inputs as octets. The first octet ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver RapidIO Interface to Pi-Sched UTXD [31:0] COMMON TRANSMIT UTXSOC FIFO WUTXCLK (60 MHz—146 MHz) PFCLK (4x OUTPUT CLOCK FROM PLL) (240 MHz—584 MHz) PLL Transmit Cell Interface The transmit interface performs ...
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Data Sheet August 2001 RapidIO Interface to Pi-Sched Table 8. RapidIO Signals to/from FPGA Interface Name (All End with _A, _B, or From _C Depending on FPGA Channel) Receive Cell Interface ZRXD<31:0> — ZRXSOC — ZRXSOCVIOL — ZRXALNVIOL — ZCLKSTAT ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver RapidIO Interface to Pi-Sched Table 9. Signals Used as Register Bits Register Bit(s) OSHLBENB Used during the internal built-in self-test mode. Indicates that the single-ended versions of the transmit module outputs ...
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Data Sheet August 2001 Memory Map (continued) Table 10. Structural Register Elements Element Register sreg Status A status register is read only, and, as the name implies, is used to convey the status Register information of a particular element or ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) This table is constructed to show the correct values when read and written via the system bus MPI interface. When using this table while interfacing with the system ...
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Data Sheet August 2001 Memory Map (continued) Table 11. Memory Map (continued) ADDR Register DB7 DB6 [7:0] Type — — 10 isreg — — 11 iereg — — 12 iareg — — 13 iereg — — 14 isreg — — ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 11. Memory Map (continued) ADDR Register DB7 DB6 [7:0] Type — — 24, 3c, sreg 54, 6c, 84, 9c, b4, cc 25, 3d, sreg Concat Concat 55, ...
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Data Sheet August 2001 Memory Map (continued) Table 11. Memory Map (continued) ADDR Register DB7 DB6 [7:0] Type — — 2a, 42, iareg 5a, 72, 8a, a2, ba, d2 2b, 43, iareg AIS AIS interrupt interrupt 5b, 73, flag flag ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 11. Memory Map (continued) ADDR Register DB7 DB6 [7:0] Type 32, 4a, counter overflow 62, 7a, 92, aa, c2, da 33, 4b, counter overflow 63, 7b, 93, ...
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Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions Bit/ Bit/Register Register Register Name(S) Location (Hex) fixed rev [0:7] 00 [0:7] fixed id lsb [0:7] 01 [0:7] fixed id msb [7:0] 02 [0:7] scratch pad [0:7] 03 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) Bit/ Register Location (Hex) serial port output MUX 09 [0] select for ch#1 serial port output MUX 09 [1] select ...
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Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Bit/Register Name(S) Location (Hex) input/output parallel bus 0C [5] parity control scrambler/descrambler 0C [6] control transmit B1 error insert 0F [0:7] mask [0: ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Name(S) Channel Register Blocks rx behavior in lof force ais-l control TOH serial output port par err ins cmd rx k1/k2 ...
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Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Bit/Register Name(S) tx mode of operation source select source select source select tx d12~d9 source select ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Bit/Register Name(S) Location (Hex) per sts-12 alarm flag 26, 3e, 56, 6e, 86, 9e, b6, ce [0] ais-p flag 26, ...
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Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Bit/Register Name(S) Location (Hex) FIFO aligner threshold 28, 40, 58, 70, error flag 88, a0, b8, d0 [0] receiver internal path par- 28, 40, 58, 70, ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/Register Bit/Register Name(S) AIS interrupt flags 12 2a, 42, 5a, 72, 8a, a2, ba, d2 AIS interrupt flags 11, ...
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Data Sheet August 2001 Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Bit/Register Name(S) Location (Hex) LVDS link b1 parity error 32, 4a, 62, counter 7a, 92, aa, b2, da [0:7] LOF counter 33, 4b, 63, 7b, ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Memory Map (continued) Table 12. Memory Map Descriptions (continued) Bit/ Register Bit/Register Name(S) Location (Hex) CDR control register 1 0xe0[6] 0xe0[5] 0xe0[4] 0xe0[3] CDR control register 1 0xe0[1] 0xe0[0] CDR control ...
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Data Sheet August 2001 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Power Supply Decoupling LC Circuit The 850 MHz HSI macro contains both analog and digital circuitry. The data recovery function, for example, is implemented as primarily a digital function, but it ...
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Data Sheet August 2001 HSI Electrical and Timing Characteristics Table 15. Absolute Maximum Ratings Parameter Power Dissipation on V A_STM DD Table 16. Recommended Operating Conditions Parameter V 15 Supply Voltage DD Junction Temperature Table 17. Receiver Specifications Parameter Input ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Parallel RapidIO-like Interface Timing Characteristics Figure 17 illustrates the timing for the receive parallel interfaces A, B, and C (DDR). The recommended operating conditions for this interface are the same as ...
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Data Sheet August 2001 Embedded Core LVDS I/O Table 22. Driver dc Data* Parameter Output Voltage High Output Voltage Low Output Differential Voltage Output Offset Voltage Output Impedance, Differential R ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Embedded Core LVDS I/O LVDS Receiver Buffer Requirements Table 25. Receiver ac Data* Parameter Pulse-width Distortion Propagation Delay Time With Common-mode Variation ( 2.4 V) Output Rise Time, 20% ...
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Data Sheet August 2001 Input/Output Buffer Measurement Conditions (on-LVDS Buffer) TO THE OUTPUT UNDER TEST A. Load Used to Measure Propagation Delay Note: Switch to V for switch to GND for T DD PLZ PZL out[i] Agere ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver LVDS Buffer Characteristics Termination Resistor The LVDS drivers and receivers operate on a 100 not required. The differential driver and receiver buffers include termination resistors inside the device package, as shown ...
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Data Sheet August 2001 Pin Information This section describes the pins and signals that perform FPGA-related functions. During configuration, the user- programmable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 29. FPGA Common-Function Pin Description (continued) Symbol I/O Special-Purpose Pins (Can also be used as a general I/O.) M[3:0] I During powerup and initialization, M0—M3 are used ...
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Data Sheet August 2001 Pin Information (continued) Table 29. FPGA Common-Function Pin Description (continued) Symbol I/O A[0:17] I During MPI mode, the A[0:17] are used as the address bus driven by the PowerPC bus master, utilizing the least significant bits ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary. Table 30. FPSC Function Pin Description Symbol I/O HSI LVDS Receive ...
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Data Sheet August 2001 Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol I/O HSI LVDS Transmit Pins txd_b_p0 I txd_b_n0 I txd_c_p0 I txd_c_n0 I txd_b_p1 I txd_b_n1 I txd_c_p1 I txd_c_n1 I txd_b_p2 I txd_b_n2 I ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol I/O HSI Test Signals tstclk I mreset I testrst I resettx I tstMUX[9:0]s O scan_tstmd I scan_en I tstsuftld I ...
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Data Sheet August 2001 Pin Information (continued) Table 30. FPSC Function Pin Description (continued) Symbol I/O RapidIO LVDS Interface Pins (Transmitter) txd_a_p<7:0> O txd_a_n<7:0> O txsoc_a_p O txsoc_a_n O txclk_a_p O txclk_a_n O txd_b_p<7:0> O txd_b_n<7:0> O txsoc_b_p O txsoc_b_n ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) In Table 31, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. Table ...
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Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O STM or 8B/10B Signals (continued) doutac<7:0> doutac_par doutac_spe doutac_c1j1 doutac_en doutac_fp doutad<7:0> doutad_par doutad_spe doutad_c1j1 doutad_en doutad_fp doutba<7:0> doutba_par doutba_spe doutba_c1j1 doutba_en ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name TOH Signals toh_clk toh_inaa toh_inab toh_inac toh_inad toh_inba toh_inbb toh_inbc toh_inbd tx_toh_ck_en toh_outaa toh_outab toh_outac toh_outad toh_outba toh_outbb ...
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Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name I/O STM Clock and Control sys_fp I System frame pulse for transmitter section. line_fp I Line frame pulse for receiver section. fpga_sysclk O ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name RapidIO Signals (Channel A) csysenb_a rstn_rx_a utxd_a<31:0> utxsoc_a rstn_utx_a utxtristn_a ytristn_a zrxd_a<31:0> zrxsoc_a zrxsocviol_a zrxalnviol_a zclkstat_a wrxclk_a_fpga RapidIO ...
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Data Sheet August 2001 Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name RapidIO Signals (Channel B) (continued) rstn_rx_b utxd_b<31:0> utxsoc_b rstn_utx_b utxtristn_b ytristn_b zrxd_b<31:0> zrxsoc_b zrxsocviol_b zrxalnviol_b zclkstat_b wrxclk_b_fpga RapidIO Signals (Channel C) csysenb_c rstn_rx_c ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 31. Embedded Core/FPGA Interface Signal Description (continued) Pin Name RapidIO Signals (Channel C) (continued) utxd_c<31:0> utxsoc_c rstn_utx_c utxtristn_c ytristn_c zrxd_c<31:0> zrxsoc_c zrxsocviol_c zrxalnviol_c zclkstat_c wrxclk_c_fpga RapidIO Signals ...
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... Note that this open pin can be used to connect signals that do not require the use of I/O registers to meet timing. — Place and route the design in both the ORT8850H and ORT8850L to verify both produce valid designs. Note that this method guarantees the Agere Systems Inc. ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout V IO VREF DD BA352 Bank Group A1 — — B1 — — C2 — — AA23 — — C1 — — ...
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Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group AC11 — — (CL (CL) 4 AE2 — — (CL ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group AB2 6 (BL) 3 AC2 6 (BL) 4 C24 — — AC1 6 (BL) ...
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Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group AE10 6 (BL) — AD11 6 (BL) 10 AE11 6 (BL) 10 AF10 6 (BL) 11 AF11 6 (BL) ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group AE19 — — AD19 — — AC19 — — AF20 — — AF21 — ...
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Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group AB26 — — Y23 — — Y24 — — Y25 — — N12 — — AA25 — — AA26 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group P16 — — R11 — — N24 — — N23 — — N25 — ...
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Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group A25 — — B24 — — A24 — — C23 — — B23 — — A23 — — D22 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group T13 — — C13 1 (TC) 4 D13 1 (TC) 4 A14 1 (TC) ...
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Data Sheet August 2001 Pin Information (continued) Table 33. ORT8850L 352-Pin PBGA Pinout (continued VREF DD BA352 Bank Group B4 0 (TL (TL — — B3 — — D3 — — D5 — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout V IO VREF DD BM680 I/O Bank Group A1 — — — — — — — — E3 — — G5 — — (TL) — ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group N5 7 (CL AM22 — — (CL (CL (CL (CL (CL) — (CL) ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AB1 7 (CL AA5 7 (CL AA3 7 (CL (CL) — AB2 7 (CL AA4 7 (CL) ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AJ3 6 (BL AK2 6 (BL AL1 6 (BL AB20 — — V AJ5 6 (BL AJ4 6 (BL AB21 — — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AK12 6 (BL AP9 6 (BL AL31 — — V AN10 6 (BL AL12 6 (BL AM11 6 (BL) ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AL19 5 (BC AP20 5 (BC AK19 5 (BC AM15 5 (BC) — AN20 5 (BC Y21 — — V AP21 5 (BC) ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group P13 — — V AL25 — — O AL26 — — O B32 — — AM26 — — O AM27 — ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AK32 — — AJ31 — — R20 — — V AL34 — — AK33 — — AJ32 — — M32 — — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group T19 — — V AC31 — — AB31 — — T34 — — V AD32 — — AD33 — ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group T32 — — R34 — — AM33 — — U30 — — T31 — — V17 — — V R33 — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group H34 — — J32 — — Y13 — — V K31 — — K30 — — H33 — ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group A29 — — O D27 — — O E26 — — O C27 — — O D26 — — O A28 — — O B27 — — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group D19 1 (TC C19 1 (TC B19 1 (TC — — V E19 1 (TC D18 1 (TC ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group C11 0 (TL B10 0 (TL (TL C10 0 (TL (TL (TL D10 0 (TL — — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AP1 — — (TL (TL (CL (CL (CL AA2 ...
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... Data Sheet August 2001 Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group P16 — — P19 — — R16 — — R17 — — R18 — — R19 — ...
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... ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Pin Information (continued) Table 34. ORT8850L and ORT8850H 680-Pin PBGAM Pinout (continued VREF DD BM680 I/O Bank Group AA20 — — V AA21 — — V AA22 — — V N21 — — V N22 — — V AB3 — ...
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Data Sheet August 2001 Package Thermal Characteristics Summary There are three thermal parameters that are in com- mon use should be noted that all JA JC, and JC , the parameters are affected, to varying degrees, by package ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Package Thermal Characteristics Table 35. ORCA ORT8850 Plastic Package Thermal Guidelines (°C/W) JA Package 0 200 500 fpm fpm fpm 352-Pin 19.0 16.0 15.0 PBGA 680-Pin 13.4 11.5 10.5 PBGAM* * ...
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Data Sheet August 2001 Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Package Outline Drawings 352-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.56 0. CENTER ARRAY G FOR THERMAL ...
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Data Sheet August 2001 Package Outline Diagrams 680-Pin PBGAM Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE 0.61 ± 0.08 0.50 ± 0. ...
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... Symbol BM Plastic Ball Grid Array, Multilayer BA Table 40. ORCA FPSC Package Matrix (Speed Grades) Device 680-Pin PBGAM BM680 –1, –2, –3 ORT8850L –1, –2, –3 ORT8850H 110 ORT8850(L)( 680 Value Temperature –40 °C to +85 °C Description Plastic Ball Grid Array Package ...
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... Data Sheet August 2001 Software Ordering Information Implementing a design in an ORT8850H/L requires the ORCA Foundry Development System and an ORT8850 FPSC Desgin Kit. For ordering information, please visit: http://www.agere.com/netcom/ipkits/ort8850/ Agere Systems Inc. Eight-Channel x 850 Mbits/s Backplane Transceiver ORCA ORT8850 FPSC 111 ...
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ORCA ORT8850 FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Motorola is a registered trademark and RapidIO is a trademark of Motorola, Inc. EIA is a registered trademark of Electronic Industries Association. IEEE is a registered trademark of The Institute of ...