ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 15

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
ORT8850 Overview
HSI Interface
The high-speed interconnect (HSI) macrocell is used
for clock/data recovery and MUX/deMUX between
106.25 MHz byte-wide internal data buses and
850 Mbits/s external serial links.
The HSI interface receives eight 850 Mbits/s serial
input data streams from the LVDS inputs and provides
eight independent 106.25 MHz byte-wide data streams
and recovered clock to the STM macro. There is no
requirement for bit alignment since SONET type fram-
ing will take place inside the ORT850 core. For trans-
mit, the HSI converts four byte-wide 106.25 MHz data
streams to serial streams at 850 Mbits/s at the LVDS
outputs.
STM Macrocell
The STM portion of the embedded core consists of
transmitter (Tx) and receiver (Rx) sections. The
receiver receives eight byte-wide data streams at
106.25 MHz and the associated clocks from the HSI. In
the Rx section, the incoming streams are SONET
framed and descrambled before they are written into a
FIFO, which absorbs phase and delay variations and
allows the shift to the system clock. The TOH is then
extracted and sent out on the eight serial ports. The
pointer mover consists of three blocks: pointer inter-
preter, elastic store, and pointer generator. The pointer
interpreter finds the synchronous transport signal
(STS) synchronous payload envelopes (SPE) and
places it into a small elastic store from which the
pointer generator will produce eight byte-wide STS-12
streams of data that are aligned to the system timing
pulse.
In the Tx section, transmitted data for each channel is
received through a parallel bus and a serial port from
the FPGA circuit. TOH bytes are received from the
serial input port and can be optionally inserted from
programmable registers or serial inputs to the STS-12
frame via the TOH processor. Each of the eight parallel
input buses is synchronized to a free-running system
clock. Then the SPE and TOH data is transferred to the
HSI.
The STM macrocell also has a scrambler/descrambler
disable feature, allowing the user to disable the scram-
bler of the transmitter and the descrambler of the
receiver. Also, unused channels can be disabled to
reduce power dissipation.
Agere Systems Inc.
(continued)
Eight-Channel x 850 Mbits/s Backplane Transceiver
8B/10B Encoder/Decoder
The ORT8850 facilitates high-speed serial transfer of
data in a variety of applications including Gigabit Ether-
net, fibre channel, serial backplanes, and proprietary
links. The device provides 8B/10B coding/decoding for
each channel. The 8B/10B transmission code includes
serial encoding/decoding rules, special characters, and
error detection.
Information to be transmitted over a fibre shall be
encoded eight bits at a time into a 10-bit transmission
character and then sent serially. The 10-bit transmis-
sion characters support all 256 eight-bit combinations.
Some of the remaining transmission characters
referred to as special characters, are used for functions
which are to be distinguishable from the contents of a
frame.
FPGA Interface
The FPGA logic will receive/transmit frame-aligned
(optional for 8B/10B mode) streams of 106.25 MHz
data (maximum of eight streams in each direction)
from/to the backplane transceiver embedded core. All
frames transmitted to the FPGA will be aligned to the
FPGA frame pulse which will be provided by the FPGA
user’s logic to the STM macro. If the receive pointer
mover and alignment FIFOs are bypassed, then each
channel will provide its own receive clock and receive
frame pulse signals. Otherwise, all frames received
from the FPGA logic will be aligned to the system
frame pulse that will be supplied to the STM macro
from the FPGA user’s logic.
Byte-Wide Parallel Interface
Three byte-wide parallel interface are provided on the
ORT8850. Each interface provides for transmit and
receive of byte-wide data, one control signal, and one
clock. Receive data is sampled on both edges of the
receive clock and is converted to a 32-bit data bus,
which is single-edge clocked by a half-speed clock for
transfer to the FPGA logic. Maximum transmit/receive
clock rate is 311 MHz and 155 MHz for the internal
FPGA clock. This allows for a 622 Mbits/s link data
transfer rate. Other functions provided include a check
for a minimum number of transferred bytes.
The first byte-wide interface (RapidIO A in Figure 2) is
always available. The other two interfaces (RapidIO B
and RapidIO C) are available when the 850 Mbits/s
serial links are not being used.
ORCA ORT8850 FPSC
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