cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 82

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
17.0 CAN Module
Each of the two CAN modules provides a Full CAN class,
CAN (Controller Area Network) serial bus interface for low/
high speed applications. They support reception and trans-
mission of extended frames with a 29-bit identifier, standard
frames with an 11-bit identifier, applications that require
high speed (up to 1 MBit/s), and a low-speed CAN interface
with CAN master capability. Data transfer between the CAN
bus and the CPU is handled by 15 message buffers, which
can be individually configured as receive or transmit buffers.
Every message buffer includes a status/control register
which provides information about its current status and ca-
pabilities to configure the buffer. All message buffers are
able to generate an interrupt on the reception of a valid
frame or the successful transmission of a frame. In addition,
an interrupt can be generated on bus errors.
An incoming message is only accepted if the message iden-
tifier passes one of two acceptance filtering masks. The fil-
tering mask can be configured to receive a single message
ID for each buffer or a group of IDs for each receive buffer.
One of the buffers uses a separate message filtering proce-
dure. This provides the capability to establish a BASIC-CAN
path. Remote transmission requests can be processed au-
tomatically by automatic reconfiguration to a receiver after
transmission or by automated transmit scheduling upon re-
ception. A priority decoder allows any buffer to have one of
16 transmit priorities including the highest or lowest abso-
lute priority, for a total of 240 different transmit priorities.
A decided bit time counter (16-bit wide) is provided to sup-
port real time applications. The contents of this counter are
captured into the message buffer RAM on reception or
transmission. The counter can be synchronized through the
CAN network. This synchronization feature allows a reset of
the counter after the reception or transmission of a mes-
sage in buffer 0.
Each CAN module is a fast CPU bus peripheral which al-
lows single-cycle byte or word read/write access. The CPU
controls the CAN module by programming the registers in
the CAN register block. This includes initialization of the
CAN baud rate, logic level of the CAN pins, and enable/dis-
able of the CAN module. A set of diagnostic features, such
as loopback, listen only, and error identification, support de-
velopment with the CAN module and provide a sophisticat-
ed error management tool.
Each CAN module implements the following features:
T CAN specification 2.0B
T 15 message buffers, each configurable as receive or
T Remote Frame support
T Acceptance filtering
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate up to 1 Mbit/s
transmit buffers
— Message buffers are 16-bit wide dual-port RAM
— One buffer may be used as a BASIC-CAN path
— Automatic transmission after reception of a Remote
— Auto receive after transmission of a RTR
Transmission Request (RTR)
82
T Programmable transmit priority
T Interrupt capability
T 16-bit counter with time stamp capability on successful
T Power Save capabilities with programmable Wake-Up
T Push-pull capability of the input/output pins
T Diagnostic functions
17.1
As shown in Figure 16, each CAN module consists of three
blocks: the CAN core, interface management, and a dual-
ported RAM containing the message buffers.
There are two dedicated device pins for each CAN interface,
CANnTX as the transmit output and CANnRX as the receive
input.
The CAN core implements the basic CAN protocol features
such as bit-stuffing, CRC calculation/checking, and error
management. It controls the transceiver logic and creates
error signals according to the bus rules. In addition, it con-
verts the data stream from the CPU (parallel data) to the se-
rial CAN bus data.
The interface management block is divided into the register
block and the interface management processor. The regis-
ter block provides the CAN interface with control information
from the CPU and provides the CPU with status information
from the CAN module. Additionally, it generates the interrupt
to the CPU.
The interface management processor is a state machine ex-
ecuting the CPU’s transmission and reception commands
and controlling the data transfer between several message
buffers and the RX/TX shift registers.
15 message buffers are memory mapped into RAM to trans-
mit and receive data through the CAN bus. Eight 16-bit reg-
isters belong to each buffer. One of the registers contains
control and status information about the message buffer
configuration and the current state of the buffer. The other
registers are used for the message identifier, a maximum of
up to eight data bytes, and the time stamp information. Dur-
ing the receive process, the incoming message will be
stored in a hidden receive buffer until the message is valid.
Then, the buffer contents will be copied into the first mes-
sage buffer which accepts the ID of the received message.
— Two filtering capabilities: global acceptance mask and
— One of the buffers uses an independent acceptance
— One interrupt vector for all message buffers (receive/
— Each interrupt source can be enabled/disabled
reception or transmission of a message
over the CAN bus (alternate source for the Multi-Input
Wake-Up module)
— Error identification
— Loopback and listen-only features for test and initial-
individual buffer identifiers
filtering procedure
transmit/error)
ization purposes
FUNCTIONAL DESCRIPTION