cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 110

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

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17.10.9 Basic Mask Register (BMSKBn/BMSKXn)
The BMSKBn and BMSKXn registers allow masking the
buffer 14, or “don’t care” the incoming extended/standard
identifier bits, RTR/XRTR, and IDE. Throughout this docu-
ment, the two 16-bit registers BMSKBn and BMSKXn are
referenced to as a 32-bit register BMSK.
The following are the bits for the BMSKB register.
The following are the bits for the BMSKX register.
For all BMSKBn and BMSKXn register bits the following ap-
plies:
0 – The incoming identifier bit must match the correspond-
1 – Accept 1 or 0 (“don’t care”) in the incoming ID bit inde-
When an extended frame is received from the CAN bus, all
BMSK bits BM28:0, IDE, RTR, and XRTR are used to mask
the incoming message. In this case, the RTR bit in the
BMSK register corresponds to the SRR bit in the message.
The XRTR bit in the BMSK register corresponds to the RTR
bit in the message.
During the reception of standard frames, only the BMSK bits
BM[28:18], RTR, and IDE are used. In this case, the
BM[28:18] bits in the BMSK register correspond to the
ID[10:0] bits in the message.
15
Basic Mask
Extended
Standard
Frame
Frame
pendent from the corresponding bit in the message
buffer ID registers. The corresponding ID bit in the mes-
sage buffer will be overwritten by the incoming identifier
bits.
15
ing bit in the message buffer identifier register.
BM28:18
BM28:18
ID28:18
ID10:0
BM14:0
5
R/W
R/W
0
0
SRR IDE
RTR IDE BM17:0 XRTR
RTR IDE
RTR
4
IDE
3
ID17:0
2
BM17:15
1
Unused
XRTR
RTR
0
0
110
17.10.10 CAN Interrupt Enable Register (CIENn)
The CIENn register enables the transmit/receive interrupts
of the message buffers 0 through 14 as well as the CAN Er-
ror Interrupt.
EIEN
IEN
17.10.11 CAN Interrupt Pending Register (CIPNDn)
The CIPNDn register indicates any CAN Receive/Transmit
Interrupt Requests caused by the message buffers 0..14
and CAN error occurrences.
EIPND
IPND
EIPND
EIEN
15
15
14
14
The Error Interrupt Enable bit allows the CAN
module to interrupt the CPU if any kind of
CAN receive/transmit errors are detected.
This causes any error status change in the er-
ror counter registers REC/TEC is able to gen-
erate an error interrupt.
0 – The error interrupt is disabled and no er-
1 – The error interrupt is enabled and a
The Buffer Interrupt Enable bits allow software
to enable/disable the interrupt source for the
corresponding message buffer. For example,
IEN14 controls interrupts from buffer14, and
IEN0 controls interrupts from buffer0.
0 – Buffer as interrupt source disabled.
1 – Buffer as interrupt source enabled.
The Error Interrupt Pending field indicates the
status change of TEC/REC and will execute
an error interrupt if the EIEN bit is set. Soft-
ware has the responsibility to clear the EIPND
bit using the CICLRn register.
0 – CAN status is not changed.
1 – CAN status is changed.
The Buffer Interrupt Pending bits are set by
the CAN module following a successful trans-
mission or reception of a message to or from
the corresponding message buffer. For exam-
ple, IPND14 corresponds to buffer14, and
IPND0 corresponds to buffer0.
0 – No interrupt pending for the correspond-
1 – Message buffer has generated an inter-
ror interrupt will be generated.
change in REC/TEC will cause an inter-
rupt to be generated.
ing message buffer.
rupt.
R/W
R
0
0
IPND
IEN
0
0