cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 146

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
20.4.2
Synchronous mode is only available for the UART0 module.
When synchronous mode is selected and the UCKS bit is
set, the UART operates from a clock received on the CKX
pin. When the UCKS bit is clear, the UART uses the clock
from the internal baud rate generator which is also driven on
the CKX pin. When the internal baud rate generator is used,
the equation for calculating the baud rate is:
1105920
1382400
1536000
115200
128000
230400
345600
460800
576000
691200
806400
921600
14400
19200
38400
56000
Baud
Rate
1200
1800
2000
2400
3600
4800
7200
9600
300
600
Synchronous Mode
16
16
16
16
16
16
12
16
11
10
10
15
13
13
10
13
11
10
O
7
8
7
7
9
8
7
9
SYS_CLK = 48 MHz
BR
2000
2000
1250
1500
1250
1111
401
625
101
125
202
250
125
49
17
25
16
N
1
8
7
7
1
4
4
1
1
=
SYS_CLK
---------------------------- -
15.5 0.44
2
5.0
2.5
2.0
9.5
1.0
1.0
1.5
1.0
5.5
2.5
1.5
1.0
1.0
2.5
3.5
1.0
1.0
1.0
1.5
1.0
8.5
1.0
1.0
3.5
3.5
P
u
N P
u
%err
0.00
0.00
0.00
0.00
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.00
0.04
0.04
0.00
0.16
0.16
0.79
0.79
0.04
0.16
1.36
0.79
0.79
Table 61 Baud Rate Programming
16
16
16
16
16
12
16
11
10
11
10
10
13
13
15
13
10
13
12
10
15
13
11
O
8
7
8
SYS_CLK = 24 MHz
2000
1250
1250
1111
750
625
101
125
303
250
101
125
25
33
16
N
5
8
7
4
1
1
2
2
2
1
2
2.5
2.0
1.0
1.5
1.0
1.0
5.5
2.5
1.0
1.0
1.5
1.0
2.5
1.0
1.0
2.5
1.0
1.0
1.0
3.5
3.5
1.0
1.0
1.0
2.5
1.0
P
146
%err
where BR is the baud rate, SYS_CLK is the System Clock,
N is the value of the baud rate divisor + 1, and P is the pres-
caler divide factor selected by the value in the UnPSR reg-
ister. Oversampling is not used in synchronous mode.
Use the same procedure to determine the values of N and
P as in the asynchronous mode. In this case, however, only
integer prescaler values are allowed.
0.00
0.00
0.00
0.01
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.00
0.10
0.16
0.00
0.16
0.79
0.16
0.79
0.79
0.79
0.16
1.36
0.79
2.34
16
16
16
12
16
16
11
10
11
10
14
10
16
13
13
11
13
10
13
14
10
13
O
7
SYS_CLK = 12 MHz
1250
1250
625
101
250
125
202
250
101
125
17
25
13
11
N
8
1
4
1
2
1
1
1
1
2.0
1.0
1.0
5.5
1.5
2.5
1.5
1.0
1.5
1.0
3.5
2.5
1.5
1.5
1.0
8.5
1.0
3.5
1.0
1.5
2.5
1.5
1.0
P
%err
0.00
0.00
0.00
0.01
0.00
0.00
0.01
0.00
0.01
0.00
0.04
0.00
0.16
0.10
0.16
0.27
0.16
0.79
0.16
0.79
0.79
0.79
0.16
13
13
13
12
16
11
10
14
16
12
11
11
O
9
7
7
8
7
7
7
9
SYS_CLK = 10 MHz
1282
1282
641
463
125
463
101
119
139
149
33
13
13
17
N
5
1
4
2
1
1
2.0
1.0
1.0
1.0
2.5
1.0
2.5
2.5
1.0
1.0
1.5
2.5
2.5
1.5
2.5
6.5
1.0
1.0
2.5
1.0
P
%err
0.00
0.00
0.00
0.01
0.00
0.01
0.01
0.04
0.08
0.13
0.21
0.16
0.16
0.04
0.79
0.16
1.36
1.36
0.79
0.47