cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 145

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

20.3.10 UART Mode Select Register 2 (UnMDSL2)
The UnMDSL2 register is a byte-wide, read/write register
that controls the sample mode used to recover asynchro-
nous data. At reset, the UnOVR register is cleared. The reg-
ister format is shown below.
USMD
20.3.11 UART Sample Position Register (UnSPOS)
The UnSPOS register is a byte-wide, read/write register that
specifies the sample position when the USMD bit in the
UnMDSL2 register is set. At reset, the UnSPOS register is
initialized to 06h. The register format is shown below.
USAMP
7
7
Reserved
The USMD bit controls the sample mode for
asynchronous transmission.
0 – UART determines the sample position au-
1 – The UnSPOS register determines the
The Sample Position field specifies the over-
sample clock period at which to take the first
of three samples for sensing the value of data
bits. The clocks are numbered starting at 0
and may range up to 15 for 16× oversampling.
The maximum value for this field is (oversam-
pling rate - 3). The table below shows the
clock period at which each of the three sam-
ples is taken, when automatic sampling is en-
abled (UnMDSL2.USMD = 0).
Oversampling Rate
tomatically.
sample position.
Reserved
4
10
11
12
13
14
15
16
7
8
9
3
USAMP
Sample Position
1
2
2
3
3
4
4
5
5
6
6
1
2
3
3
4
4
5
5
6
6
7
7
USMD
0
0
3
4
4
5
5
6
6
7
7
8
8
145
20.4
The UART baud rate is determined by the System Clock fre-
quency and the values in the UnOVR, UnPSR, and Un-
BAUD registers. Unless the System Clock is an exact
multiple of the baud rate, there will be a small amount of er-
ror in the resulting baud rate.
20.4.1
The equation to calculate the baud rate in asynchronous
mode is:
where BR is the baud rate, SYS_CLK is the System Clock,
O is the oversample rate, N is the baud rate divisor + 1, and
P is the prescaler divisor selected by the UPSR register.
Assuming a System Clock of 5 MHz, a desired baud rate of
9600, and an oversample rate of 16, the N × P term accord-
ing to the equation above is:
The N × P term is then divided by each Prescaler Factor
from Table 59 to obtain a value closest to an integer. The
factor for this example is 6.5.
The baud rate register is programmed with a baud rate divi-
sor of 4 (N = baud rate divisor + 1). This produces a baud
clock of:
Note that the percent error is much lower than would be pos-
sible without the non-integer prescaler factor. Error greater
than 3% is marginal and may result in unreliable operation.
Refer to Table 61 below for more examples.
BAUD RATE CALCULATIONS
Asynchronous Mode
%error
BR
The USAMP field may be used to override the
automatic selection, to choose any other clock
period at which to start taking the three sam-
ples.
N P
N
u
=
=
32.552
----------------- -
=
-----------------------------------
BR
=
16 5
6.5
------------------------------------------------ -
------------------------------ -
9615.385 9600
5
u
16
=
u10
5
u
----------------------------- -
u10
SYS_CLK
u
=
O N
6
9600
9600
6.5
5.008 (N = 5)
u
6
–
u
=
=
P
9615.385
32.552
=
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