cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 113

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

DRIVE
17.10.17 CAN Timer Register (CTMRn)
The CTMRn register reports the current value of the Time
Stamp Counter as described in Section 17.8.
The CTMRn register is a free running 16-bit counter. It con-
tains the number of CAN bits recognized by the CAN mod-
ule since the register has been cleared. The counter starts
to increment from the value 0000b after a hardware reset. If
the Timer Stamp Enable bit (TSTPEN) in the CGCRn regis-
ter is set, the counter will also be cleared on a message
transfer of the message buffer 0.
The contents of CTMR are captured into the Time Stamp
register of the message buffer after successfully sending or
receiving a frame, as described in “Time Stamp Counter” on
page 99.
17.11
After system start-up, all CAN-related registers are in their
reset state. The CAN module can be enabled after all con-
figuration registers are set to their desired value. The follow-
ing initial settings must be made:
T Configure the CAN Timing register (CTIM). See “Bit
T Configure every buffer to its function as receive/transmit.
T Set the acceptance filtering masks. See “Acceptance Fil-
T Enable the CAN interface. See “CAN Global Configura-
Before disabling the CAN module, software must make sure
that no transmission is still pending.
Note: Activity on the CAN bus can wake up the device from
a reduced-power mode by selecting the CANnRX pin as an
input to the Multi-Input Wake-Up module. In this case, the
CAN module must not be disabled before entering the re-
duced-power mode. Disabling the CAN module also dis-
ables the CANnRX pin. As an alternative, the CANnRX pin
can be connected to any other input pin of the Multi-Input
Wake-Up module. This input channel must then be config-
ured to trigger a wake-up event on a falling edge (if a domi-
nant bit is represented by a low level). In this case, the CAN
module can be disabled before entering the reduced-power
mode. After waking up, software must enable the CAN mod-
ule again. All configuration and buffer registers still contain
the same data they held before the reduced-power mode
was entered.
15
Time Logic” on page 90.
See “Buffer Status/Control Register (CNSTAT)” on
page 101.
tering” on page 92.
tion Register (CGCRn)” on page 106.
SYSTEM START-UP AND MULTI-INPUT
WAKE-UP
The Drive bit shows the output value on the
CANTX pin at the time of the error. Note that
a receiver will not drive the bus except during
ACK and during an active error flag.
CTMR15:0
R
0
0
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17.11.1 External Connection
The CAN module uses the CANnTX and CANnRX pins to
connect to the physical layer of the CAN interface. They pro-
vide the functionality described in Table 54.
The logic levels are configurable by the CTX and CRX bits
of the Global Configuration Register CGCRn (see “CAN
Global Configuration Register (CGCRn)” on page 106).
17.11.2 Transceiver Connection
An external transceiver chip must be connected between
the CAN block and the bus. It establishes a bus connection
in differential mode and provides the driver and protection
requirements. Figure 46 shows a possible ISO-High-Speed
configuration
17.11.3 Timing Requirements
Processing messages and updating message buffers re-
quire a certain number of clock cycles, as shown in
Table 55. These requirements may lead to some restrictions
regarding the Bit Time Logic settings and the overall CAN
performance which are described below in more detail. Wait
cycles need to be added to the cycle count for CPU access
to the object memory as described in CPU Access to CAN
Registers/Memory on page 100. The number of occurrenc-
es per frame is dependent on the number of matching iden-
tifiers.
Signal Name
CANnRX
CR16CAN
CANnTX
CPU Bus
CANnTX
CANnRX
Figure 46. External Transceiver
.
Table 54 External CAN Pins
Output
Type
Input
5
4
1
REF
RX
TX
Transceiver Chip
8
RS
Receive data from the CAN bus
Transmit data to the CAN bus
BUS_H
BUS_L
GND
2
VCC
3
7
6
Description
VCC
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120
120
Termination
CAN bus
signals
To other
modules
DS282