cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 151

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

21.3
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MWCS is
inactive. Data transfer is enabled when MWCS is active.
The slave starts driving MDIDO when MWCS is active. The
most significant bit (lower byte in 8-bit mode or upper byte
in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the
ECHO bit is set, the data received from MDODI is transmit-
ted on MDIDO in addition to being shifted to MWDAT. If the
ECHO bit is clear, the data transmitted on MDIDO is the
data held in the MWDAT register, regardless of its validity.
The master may negate the MWCS signal to synchronize
the bit count between the master and the slave. In the case
that the slave is the only slave in the system, MWCS can be
tied to ground.
SLAVE MODE
151
21.4
Interrupts may be enabled for any of the conditions shown
in Table 63.
Figure 71 illustrates the interrupt generation logic of this
module.
Condition
Buffer Full
Not Busy
Overrun
Table 63 Microwire Interrupt Trigger Condition
Read
INTERRUPT GENERATION
OVR = 1
RBF = 1
BSY = 0
Figure 71. MWSPI Interrupts
Bit in the
MWSTAT
Register
Status
BSY
RBF
OVF
EIW
EIO
EIR
Enable Bit
MWCTRL1
Interrupt
Register
in the
EIW
EIR
EIO
The shifter is ready
for the next data
transfer sequence.
The read buffer is
full and waiting to be
unloaded.
A new data transfer
sequence started
while both the shifter
and the read buffer
were full.
Description
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MWSPI
Interrupt
DS073