cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 70

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

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14.1.6
The PxHDRV register is a byte-wide, read/write register that
controls the slew rate of the corresponding pins. The high
drive strength function is enabled when the corresponding
bits of the PxHDRV register are set. In both GPIO and alter-
nate function modes, the drive strength function is enabled
by the PxHDRV registers. At reset, the PxHDRV registers
are cleared, making the ports low speed.
PxHDRV
14.1.7
The PxALTS register selects which of two alternate func-
tions are selected for the port pin. These bits are ignored
unless the corresponding PxALT bits are set. Each port pin
can be controlled independently.
PxALTS
7
7
Port High Drive Strength Register (PxHDRV)
Port Alternate Function Select Register
(PxALTS)
Port Pin
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
Table 30 Alternate Function Select
The PxHDRV bits control whether output pins
are driven with slow or fast slew rate.
0
1
The PxALTS bits select among two alternate
functions. Table 30 shows the mapping of the
PxALTS bits to the alternate functions. Un-
used PxALTS bits must be clear.
–
–
Slow slew rate.
Fast slew rate.
PxHDRV
PxALTS
UART0 RXD0
UART0 TXD0
UART0 CTS
UART0 CKX
PxALTS = 0
UART0 RTS
CAN1RX
CAN1TX
MDIDO
MDODI
MWCS
SRFS
MSK
SCK
PxALTS = 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TIO1
TIO2
TIO3
TIO4
TIO5
NMI
TB
0
0
70
14.2
A port pin can be configured to operate as an inverting
open-drain output buffer. To do this, the CPU must clear the
bit in the data output register (PxDOUT) and then use the
port direction register (PxDIR) to set the value of the port
pin. With the direction register bit set (direction = out), the
value zero is forced on the pin. With the direction register bit
clear (direction = in), the pin is placed in the TRI-STATE
mode. If desired, the internal weak pull-up can be enabled
to pull the signal high when the output buffer is in TRI-
STATE mode.
OPEN-DRAIN OPERATION
Port Pin
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PF5
PF6
PF7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
Table 30 Alternate Function Select
UART1 RXD1
UART2 RXD2
UART3 RXD3
UART1 TXD1
UART2 TXD2
UART3 TXD3
PxALTS = 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAN0RX
CAN0TX
ASYNC
WUI10
WUI18
WUI19
WUI20
WUI21
WUI22
WUI23
WUI24
STD
SRD
SFS
TA
PxALTS = 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRCLK
WUI11
WUI12
WUI13
WUI14
WUI15
WUI16
WUI17
WUI9
TIO6
TIO7
TIO8