cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 3

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

2.0
CPU Features
T Fully static RISC processor core, capable of operating
T Minimum 41.7 ns instruction cycle time with a 24-MHz in-
T 47 independently vectored peripheral interrupts
On-Chip Memory
T 256K bytes reprogrammable Flash program memory
T 8K bytes Flash data memory
T 32K bytes of static RAM data memory
T Addresses up to 12M bytes of external memory
Broad Range of Hardware Communications Peripherals
T ACCESS.bus serial bus (compatible with Philips I
T Dual CAN interface with 15 message buffers conforming
T 8/16-bit SPI, Microwire/Plus serial interface
T Four-channel Universal Asynchronous Receiver/Trans-
T Advanced Audio Interface (AAI) to connect to external 8/
T CVSD/PCM converter supporting one bidirectional audio
General-Purpose Hardware Peripherals
T 12-bit A/D Converter (ADC)
T Dual 16-bit Multi-Function Timer (MFT)
T Versatile Timer Unit with four subsystems (VTU)
T Four-channel DMA controller
T Timing and Watchdog Unit
T Random Number Generator peripheral
CP3CN23 Connectivity Processor Selection Guide
CP3CN23G18NEP
CP3CN23G18NEPNOPB
CP3CN23G18NEPX
CP3CN23G18NEPXNOPB
CP3CN23Y98NEP
CP3CN23Y98NEPNOPB
CP3CN23Y98NEPX
CP3CN23Y98NEPXNOPB
NEP - Erased part (serial number in Information Block 1); X - Tape and reel; NOPB - No lead solder
from 0 to 24 MHz with zero wait/hold states
ternal clock frequency, based on a 12-MHz external input
to CAN specification 2.0B active
mitter (UART), one channel has USART capability
13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)
connection
Features
NSID
Speed
(MHz)
24
24
24
24
24
24
24
24
Temp. Range
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
2
C bus)
Program
(Kbytes)
Flash
256
256
256
256
256
256
256
256
3
Extensive Power and Clock Management Support
T On-chip Phase Locked Loop
T Support for multiple clock options
T Dual clock and reset
T Power-down modes
Flexible I/O
T Up to 56 general-purpose I/O pins (shared with on-chip
T Programmable I/O pin characteristics: TRI-STATE out-
T Schmitt triggers on general-purpose inputs
T Multi-Input Wake-Up (MIWU) capability
Power Supply
T I/O port operation at 2.5V to 3.3V
T Core logic operation at 2.5V
T On-chip power-on reset
Temperature Range
T -40°C to +85°C (Industrial)
Packages
T LQFP-128, LQFP-144
Complete Development Environment
T Pre-integrated hardware and software support for rapid
T Integrated environment
T Project manager
T Multi-file C source editor
T High-level C source debugger
T Comprehensive, integrated, one-stop technical support
peripheral I/O)
put, push-pull output, weak pull-up input, high-imped-
ance input
prototyping and production
(Kbytes)
Flash
Data
8
8
8
8
8
8
8
8
(Kbytes)
SRAM
32
32
32
32
32
32
32
32
External
Address
Lines
23
23
23
23
0
0
0
0
I/Os
56
56
56
56
50
50
50
50
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LQFP-128
LQFP-128
LQFP-128
LQFP-128
LQFP-144
LQFP-144
LQFP-144
LQFP-144
Package
Type