cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 40

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
8.5.16
The FMRCV/FSMRCV register is a byte-wide read/write
register that controls the recovery delay time between two
flash memory accesses. Software must not modify this reg-
ister while a program/erase operation is in progress (FM-
BUSY set). At reset, this register is initialized to 04h if the
flash memory is idle. The CPU bus master has read/write
access to this register.
FTRCV
8.5.17
The FMAR0/FSMAR0 register contains a copy of the Func-
tion Word from Information Block 0. The Function Word is
sampled at reset. The CPU bus master has read-only ac-
cess to this register. The FSMAR0 register has the same
value as the FMAR0 register
15
7
Flash Memory Recovery Time Reload Register
(FMRCV/FSMRCV)
FSMAR0)
Flash Memory Auto-Read Register 0 (FMAR0/
The Flash Timing Recovery Delay Count field
specifies a delay of (FTRCV + 1) prescaler
output clocks.
Reserved
FTRCV
0
0
40
8.5.18
The FMAR1 register contains a copy of the Protection Word
from Information Block 1. The Protection Word is sampled
at reset. The contents of the FMAR1 register define the cur-
rent Flash memory protection settings. The CPU bus mas-
ter has read-only access to this register. The FSMAR1
register has the same value as the FMAR1 register. The for-
mat is the same as the format of the Protection Word (see
Section 8.4.2).
8.5.19
The FMAR2 register is a word-wide read-only register,
which is loaded during reset. It is used to build the Code
Area start address. At reset, the CPU executes a branch,
using the contents of the FMAR2 register as displacement.
The CPU bus master has read-only access to this register.
The FSMAR2 register has the same value as the FMAR2
register.
CADR10:0
CADR14:11 The Code Area Start Address (bits 14:11) are
CADR15
WRPROT RDPROT ISPE EMPTY BOOTAREA 1
CADR15
15
7
15
13
Flash Memory Auto-Read Register 1 (FMAR1/
FSMAR1)
Flash Memory Auto-Read Register 2 (FMAR2/
FSMAR2)
The Code Area Start Address (bits 10:0) con-
tains the lower 11 bits of the Code Area start
address. The CADR10:0 field has a fixed val-
ue of 0.
loaded during reset with the inverted value of
BOOTAREA3:0.
The Code Area Start Address (bits 15) con-
tains the upper bit of the Code Area start ad-
dress. The CADR15 field has a fixed value of
0.
14
12
CADR14:11
10
CADR7:0
9
7
6
11
4
10
CADR10:8
3
1
0
8
0