cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 150

• Manufacturer Part Number: cp3cn23
• Description: Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
• Manufacturer: National Semiconductor Corporation

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21.2
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the MWDAT register, eight or
sixteen MSK clocks, depending on the mode selected, are
MASTER MODE
Data Out
Data Out
Data In
Data In
Data Out
Data Out
MSK
MSK
Data In
Data In
MSK
MSK
Shift
Out
MSB
MSB
MSB
MSB
Shift
Out
Sample
Point
Sample
Point
MSB
MSB
MSB
MSB
Sample
Point
Sample
Point
Shift
Out
Shift
Out
MSB - 1
MSB - 1
MSB - 1
MSB - 1
Figure 69. Alternate Mode (SCIDL = 0)
Figure 70. Alternate Mode (SCIDL = 1)
Figure 67. Normal Mode (SCIDL = 0)
Figure 68. Normal Mode (SCIDL = 1)
MSB - 1
MSB - 1
MSB - 1
MSB - 1
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
150
generated to shift the 8 or 16 bits of data, and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
(LSB)
(LSB)
Bit 0
Bit 0
(LSB)
(LSB)
Bit 0
Bit 0
End of Transfer
End of Transfer
(LSB)
(LSB)
(LSB)
(LSB)
Bit 0
Bit 0
Bit 0
Bit 0
End of Transfer
End of Transfer
DS072
DS069
DS070
DS071