stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 74

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.30 - Interrupt Mask Register - IMR (3A)H
IM13/0 : INTERRUPT MASK 0/7
VIII.31 - Time Register - TIMR (3C)H
This programmable register indicates the time at the end of which the Watch Dog delivers logic ”1” on the
pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the
help of WDR bit of IDCR Identification and Dynamic Command Register) during the time defined by the
Timer Register.
The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM)
is generated at each period defined by the Timer Register if the microprocessor does not reset the counter
with the help of WDR (bit of IDCR).
When TSV=1{Time Stamping Validated (GCR)} this programmable register is not used.
VIII.32 - Test Register - TR (3E)H
T15/0 : Test bits 0/15
74/83
bit15
bit15
bit15
Nu
S3
Nu
S2
0 to 5s
When IM0 = 1, HDLC bit is masked.
When IM1 =1, C/IRX bit is masked.
When IM2 = 1, MRX bit is masked.
When IM3 = 1, MTX bit is masked.
When IM4 = 1, ICOV bit is masked
When IM5 = 1, RxFWAR bit is masked.
When IM6 = 1, RxFOV bit is masked.
When IM7 = 1, TxFWAR bit is masked.
When IM8 = 1, TxFOV bit is masked.
When IM9 = 1, INTFWAR bit is masked.
When IM10 = 1, INTFOV bit is masked.
When IM11 = 1, TIM bit is masked.
When IM12 = 1, PRSR bit is masked.
When IM13 = 1, SFCO bit is masked.
These bits are reserved for the test of the circuit in production
IM13
S1
IM12
S0
IM11
MS9
IM10
MS8
After reset (0800)
MS7
IM9
After reset (FFFF)
MS6
IM8
bit8
bit8
bit8
MS5
IM7
bit7
bit7
0 to 999ms
bit7
H
id 512ms
H
MS4
IM6
MS3
IM5
MS2
IM4
MS1
IM3
MS0
IM2
MM1
IM1
3x0.25ms
0 to
MM0
bit 0
bit 0
bit 0
IM0