stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 58

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H
ST(i)0 : STEP0 for each Output Multiplex i(0
ST(i)1 : STEP1 for each Output Multiplex i(0
DEL(i); : DELAYED Multiplex i(0
OMV (i) : Output Multiplex Validated 0/7
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H
IMTD : Increased Minimum Throughput Delay
TS0
TS1
SGV
SAV
SGC
58/83
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0
bit15
bit15
Nu
: Tristate 0
: Tristate 1
: Pseudo Random Sequence Generator Validated
: Pseudo Random Sequence analyzer Validated
: Pseudo Random Sequence Generator Corrupted
Nu
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.
OMVi =1, condition to have DOUTi pin active (0
OMVi =0, DOUTi pin is High Impedance continuously (0
When SI = 0 (bit of CMDR, variable delay mode) :
IMTD = 1, the minimum delay through the matrixmemoryis three time slots whateverthe selected
TDM output.
IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected
TDM output.
TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : ”0” is at low impedance, ”1” is at low
impedance and the third state is high impedance.
TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain : ”0” is at low impedance, ”1” is at high
impedance.
TS1 = 1, the DOUT4/5 pins are tristate : ”0” is at low impedance, ”1” is at low impedance and
the third state is high impedance.
TS1 = 0, the DOUT4/5 pins are open drain : ”0” is at low impedance, ”1” is at high impedance.
SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the
related time slot(s).
SGV = 0, PRS Generator is reset.”0” are transmitted during the related time slot.
SAV = 1, PRS analyzer is validated.
SAV = 0, PRS analyzer is reset.
When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted.
When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically.
DEL (i) ST (i) 1 ST (i) 2
X
1
1
1
0
0
0
Nu
Nu
0
0
1
1
0
1
1
Nu
0
1
0
1
1
0
1
Nu
Each bit is transmitted on the rising edge of the double clock without delay.
Bit 0 is defined by Frame synchronization Signal.
Each bit is transmitted with 1/2 bit-time delay.
Each bit is transmitted with 1 bit-time delay.
Each bit is transmitted with 2 bit-time delay.
Each bit is transmitted with 1/2 bit-time advance.
Each bit is transmitted with 1 bit-time advance
Each bit is transmitted with 2 bit-time advance.
i
7).
Nu
After reset (0000)
After reset (0000)
STEP for each Output Multiplex 0/7 delayed or not
bit8
bit8
Nu
i
i
7), delayed or not.
7), delayed or not.
bit7
bit7
Nu
H
H
i
ME
7).
SGC
i
7).
SAV
SGV
TS1
TS0
IMTD
bit 0
bit 0