stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 21

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

III - FUNCTIONAL DESCRIPTION (continued)
III.1.6 - Connection Memory
III.1.6.1 - Description
The connection memory is composed of 256 loca-
tions addressed by the number of OTDM and TS
(8x32).
Each location permits :
- to connect each input time slot to one output time
- to selectthe variable delay mode or the sequence
- to loop back an output time slot. In this case the
- to output the contents of the corresponding con-
- to output the sequence of the pseudo random
- to define the source of a sequenceby the pseudo
- to assert a high impedance level on an output
- to deliver a programmable 256-bit sequence dur-
III.1.6.2 - Access to Connection Memory
Supposing that the Switching Matrix Configuration
Register (SMCR) has been already written by the
microprocessor, it is possible to access to the con-
nection memory from microprocessor with the help
of two registers :
- Connection Memory Data Register (CMDR) and
- Connection Memory Address Register (CMAR).
III.1.6.3 - Access to Data Memory
To extract the contents of the data memory it is
possible to read the data memory from microproc-
essor with the help of the two registers :
- Connection Memory Data Register (CMDR) and
slot (If two or more output time slots are con-
nected to the same input time slot number, there
is broadcasting).
integrity mode for any time slot.
contents of an input time slot (ITSx, ITDMp) is the
same as the output time slot (OTSx,OTDMp).
nection memory instead of the data which has
been stored in data memory.
sequence generator on an output time slot: a
pseudo random sequence can be inserted in one
or several time slots (hyperchannel) of the same
Output TDM ; this insertion must be enabled by
the microprocessor in the configuration register
of the matrix.
random sequence analyzer: a pseudo random
sequence can be extracted from one or several
time slots (hyperchannel)of the same Input TDM
and routed to the analyzer; this extraction can be
enabled by the microprocessor in the configura-
tion register of the matrix (SMCR).
time slot (disconnection).
ing 125 microsecondson the Programmable syn-
chronization Signal pin (PSS).
- Connection Memory Address Register (CMAR).
III.2 - HDLC Controller
III.2.1 - Function Description
The internal HDLC controller can run up to 32
channels in a conventional HDLC mode or in a
transparent (non-HDLC) mode (configurable per
channel).
Each channel bit rate is programmable from 4kbit/s
to 64kbit/s. All the configurations are also possible
from 32 channels (from 4 to 64 kbit/s) to one
channel at 2 Mbit/s.
In reception,the HDLC time slots can directly come
from the input TDM DIN8 (direct HDLC Input) or
from any other TDM input after switching towards
the output 7 of the matrix (configurable per time
slot).
In transmission, the HDLC frames are sent on the
output DOUT6 and on the output CB (with or with-
out contention mechanism), or are switched to-
wards the other TDM output via the input 7 of the
matrix (see Figure 8 on Page 22 and Paragraph
III.2.2 on Page 23).
III.2.1.1 - Format of the HDLC Frame
The format of anHDLC frame isthe same in receive
and transmit direction and shown here after.
III.2.1.2 - Composition of an HDLC Frame
- Opening Flag
- One or two bytes for address recognition (recep-
- Data bytes with bit stuffing
- Frame Check Sequence: CRC with polynomial
- Closing Flag.
tion) and insertion (transmission)
G(x) = x16 +x12+x5+1
Command Field (second byte)
Address Field (second byte)
Command Field (first byte)
Address Field (first byte)
FCS (second byte)
Data (first byte)
Data (last byte)
FCS (first byte)
Data (optional)
Opening Flag
Closing Flag
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