stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 39

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

V - CLOCK TIMING (continued)
V.2 - TDM Synchronization
Figure 28 : Synchronization Signals received by the Multi-HDLC
Symbol
t1
t2
t3
t4
t5
t6
t7
t7
t8
t9
Clock Period if 4096kHz
Clock Period if 2048kHz
Delay between CLOCK A or B and DCLK (30pF)
Set-up Time FS/DCLK
Hold Time FS/DCLK
Duration FS
DCLK to Data 50pF
DCLK to Data 100pF
Set-up Time Data/DCLK
Hold Time Data/DCLK
Set-up Echo/DCLK (rising edge)
Hold Time Echo/DCLK (rising edge)
CLOCK A (o r B)
DCLK de live re d by
the Multi-HDLC
FSCG d e livered by
the Multi-HDLC
DOUT0/7, CB
DIN0/8
ECHO
The four Multiplex Configura tion Re giste rs a re a t z e ro (no de lay be twe e n FS a nd Multiplexe s).
Parameter
Bit 7, Time S lot 31
t2
t3
t6
Bit 0, Time Slot 0
Id CLOCKA or B
t1
t5
t7
t4
Min.
244
205
20
20
20
20
t8
t9
Typ.
244
488
t7
5
Id CLOCKA or B
125000-244
t1-20
Max.
100
155
30
50
STLC5464
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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